Abstract:
Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a capping layer (16) and a dielectric layer (18). The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor (14). In the process of sputter etching, the capping layer is redeposited (22) onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.
Abstract:
PROBLEM TO BE SOLVED: To provide an interconnection structure with improved adhesion between a noble metal liner and dielectric material adjacent thereto. SOLUTION: The structure relates to the interconnection structure with improved adhesion between a chemically etched dielectric material and a noble metal liner, as well as a method for manufacturing the structure. The structure includes a step of processing the chemically etched dielectric material to change chemical properties of the dielectric material so that the processed surface can become hydrophobic. The processing step is carried out before deposition of the noble metal liner, whereby the adhesion between the chemically etched dielectric material and the noble metal liner can be improved. COPYRIGHT: (C)2008,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide a phase change memory element connected to the edge part of a thin film electrode, and to provide a method of manufacturing the same. SOLUTION: A phase change memory (PCM) cell structure includes a first electrode 60E, a phase change element 70E, and a second electrode 80E, wherein the phase change element 70E is inserted between the first electrode 60E and the second electrode 80E, and only an edge part 75 of the first electrode 60E is contacted with the phase change element 70E, thereby reducing a contact area between the phase change element 70E and the first electrode 60E to increase a current density flowing through the phase change element 70E and effectively cause a phase change by a first programming power by a comparatively small current. COPYRIGHT: (C)2008,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide an improved process for manufacturing a via applicable to a requirement in the latest scaling technique, and capable of manufacturing the appropriately operable via in a batch. SOLUTION: The via and its manufacturing technique are provided with the improved high aspect ratio. In one embodiment, the manufacturing method is provided for the copper-plated via of the improved high aspect ratio. The method includes a step of etching the via of the high aspect ratio into a dielectric layer, for depositing a diffusion barrier region in the via of the high aspect ratio and on one or a plurality of surfaces of the dielectric layer, for depositing a copper layer on the diffusion barrier layer, for depositing a ruthenium layer on the copper layer, and for filling the via of the high aspect ratio with the plated copper on the ruthenium layer. Also, the via of the high aspect ratio is provided as copper-plated according to the method. COPYRIGHT: (C)2010,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide an interconnect structure having electromigration resistance enhanced by lining the inside of a lower portion of a via opening inside with a multi-layered liner. SOLUTION: The multi-layered liner includes, from the patterned surface of a dielectric material outwards, a diffusion barrier, a multi-material layer and a metal-containing hard mask. The multi-material layer includes a first material layer comprised of residue from an underlying dielectric capping layer, and a second material layer comprised of residue from an underlying metallic capping layer. The present invention also provides a method of fabricating such an interconnect structure which includes the multi-layered liner within the lower portion of the via opening formed within a dielectric material. COPYRIGHT: (C)2010,JPO&INPIT
Abstract:
A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer. As such, when current is provided to the fuse structure electromigration of the conductive material occurs and over time an opening is formed in the conductive material blowing the fuse element.
Abstract:
An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof, and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen/nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen/nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed.
Abstract:
A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.
Abstract:
A MEM switch is described having a free moving element (140) within in micro-cavity (40), and guided by at least one inductive element. The switch consists of an upper inductive coil (170); an optional lower inductive coil (190), each having a metallic core (180,200) preferably made of permalloy; a micro-cavity (40); and a free-moving switching element (140) also made of magnetic material. Switching is achieved by passing a current through the upper coil, inducing a magnetic field in the coil element. The magnetic field attracts the free-moving magnetic element upwards, shorting two open wires (M_I M_r) and thus, closing the switch. When the current flow stops or is reversed, the free-moving magnetic element drops back by gravity to the bottom of the micro-cavity and the wires open. When gravity cannot be used, a lower coil becomes necessary to pull the free-moving switching element back and holding it at its original position.
Abstract:
Interconnect structures having self-aligned dielectric caps are provided. At least one metallization level is formed on a substrate. A dielectric cap is selectively deposited on the metallization level.