公开(公告)号：WO2004053979A8

公开(公告)日：2005-05-12

申请号：PCT/EP0350957

申请日：2003-12-08

Applicant: IBM ,  IBM DEUTSCHLAND ,  INFINEON TECHNOLOGIES AG

Inventor： CLEVENGER LARRY ,  DALTON TIMOTHY ,  HOINKIS MARK ,  KALDOR STEFFEN ,  KUMAR KAUSHIK ,  LA TULIPE DOUGLAS JR ,  SEO SOON-CHEON ,  SIMON ANDREW ,  WANG YUN-YU ,  YANG CHIH-CHAO ,  YANG HAINING

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L21/76835 ,  H01L21/76844 ,  H01L21/76847 ,  H01L21/76865

Abstract: Disclosed is a method for depositing a metal layer on an interconnect structure for a semiconductor wafer. In the method, a metal conductor (14) is covered by a capping layer (16) and a dielectric layer (18). The dielectric layer is patterned so as to expose the capping layer. The capping layer is then sputter etched to remove the capping layer and expose the metal conductor (14). In the process of sputter etching, the capping layer is redeposited (22) onto the sidewall of the pattern. Lastly, at least one layer is deposited into the pattern and covers the redeposited capping layer.

Abstract translation: 公开了一种用于在半导体晶片的互连结构上沉积金属层的方法。 在该方法中，金属导体（14）被覆盖层（16）和电介质层（18）覆盖。 对电介质层进行图案化以使覆盖层露出。 然后溅射蚀刻覆盖层以去除覆盖层并暴露金属导体（14）。 在溅射蚀刻的过程中，将覆盖层再沉积（22）到图案的侧壁上。 最后，至少一层沉积到图案中并覆盖再沉积的覆盖层。

公开(公告)号：JP2007318141A

公开(公告)日：2007-12-06

申请号：JP2007135218

申请日：2007-05-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： LIN QINGHUANG ,  YANG CHIH-CHAO ,  SPOONER TERRY A ,  GRISELDA BONILLA

IPC: H01L21/768 ,  H01L21/312 ,  H01L21/316 ,  H01L21/3205 ,  H01L23/52

CPC classification number: H01L23/53295 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76831 ,  H01L21/76843 ,  H01L21/76844 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an interconnection structure with improved adhesion between a noble metal liner and dielectric material adjacent thereto.
SOLUTION: The structure relates to the interconnection structure with improved adhesion between a chemically etched dielectric material and a noble metal liner, as well as a method for manufacturing the structure. The structure includes a step of processing the chemically etched dielectric material to change chemical properties of the dielectric material so that the processed surface can become hydrophobic. The processing step is carried out before deposition of the noble metal liner, whereby the adhesion between the chemically etched dielectric material and the noble metal liner can be improved.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供具有改进的贵金属衬垫和与其相邻的电介质材料之间的粘附性的互连结构。 解决方案：该结构涉及具有改进的化学蚀刻介电材料和贵金属衬垫之间的粘附性的互连结构以及制造该结构的方法。 该结构包括处理化学蚀刻的电介质材料以改变电介质材料的化学性质以使经处理的表面变得疏水的步骤。 在沉积贵金属衬垫之前进行处理步骤，从而可以改善化学蚀刻的电介质材料和贵金属衬垫之间的粘合性。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007273988A

公开(公告)日：2007-10-18

申请号：JP2007086288

申请日：2007-03-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： WONG KEITH KWONG HON ,  ARNOLD JOHN CHRISTOPHER ,  GAIDIS MICHAEL CHRISTOPHER ,  RADENS CARL JOHN ,  YANG CHIH-CHAO ,  HSU LOUIS LU-CHEN ,  DALTON TIMOTHY JOSEPH ,  CLEVENGER LAWRENCE A

IPC: H01L27/105 ,  H01L45/00

CPC classification number: H01L45/1675 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: PROBLEM TO BE SOLVED: To provide a phase change memory element connected to the edge part of a thin film electrode, and to provide a method of manufacturing the same.
SOLUTION: A phase change memory (PCM) cell structure includes a first electrode 60E, a phase change element 70E, and a second electrode 80E, wherein the phase change element 70E is inserted between the first electrode 60E and the second electrode 80E, and only an edge part 75 of the first electrode 60E is contacted with the phase change element 70E, thereby reducing a contact area between the phase change element 70E and the first electrode 60E to increase a current density flowing through the phase change element 70E and effectively cause a phase change by a first programming power by a comparatively small current.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供连接到薄膜电极的边缘部分的相变存储元件，并提供其制造方法。 解决方案：相变存储器（PCM）单元结构包括第一电极60E，相变元件70E和第二电极80E，其中相变元件70E插入在第一电极60E和第二电极80E之间 并且只有第一电极60E的边缘部分75与相变元件70E接触，从而减小相变元件70E和第一电极60E之间的接触面积，以增加流过相变元件70E的电流密度和 通过相对小的电流有效地引起第一编程功率的相位变化。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2010010642A

公开(公告)日：2010-01-14

申请号：JP2008268013

申请日：2008-10-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MCFEELY FENTON R ,  YANG CHIH-CHAO

IPC: H01L21/768 ,  C23C28/00 ,  H01L21/3065 ,  H01L21/3205 ,  H01L23/52

CPC classification number: H01L21/76843 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an improved process for manufacturing a via applicable to a requirement in the latest scaling technique, and capable of manufacturing the appropriately operable via in a batch. SOLUTION: The via and its manufacturing technique are provided with the improved high aspect ratio. In one embodiment, the manufacturing method is provided for the copper-plated via of the improved high aspect ratio. The method includes a step of etching the via of the high aspect ratio into a dielectric layer, for depositing a diffusion barrier region in the via of the high aspect ratio and on one or a plurality of surfaces of the dielectric layer, for depositing a copper layer on the diffusion barrier layer, for depositing a ruthenium layer on the copper layer, and for filling the via of the high aspect ratio with the plated copper on the ruthenium layer. Also, the via of the high aspect ratio is provided as copper-plated according to the method. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于制造适用于最新缩放技术的要求的通路的改进方法，并且能够批量制造适当可操作的通孔。

解决方案：通孔及其制造技术具有改进的高纵横比。 在一个实施例中，为镀铜通孔提供改进的高纵横比的制造方法。 该方法包括将高纵横比的通孔蚀刻成电介质层的步骤，用于在高纵横比的通孔中以及介电层的一个或多个表面上沉积扩散阻挡区域，以沉积铜 层，用于在铜层上沉积钌层，并且用铀层上的镀铜填充高纵横比的通孔。 此外，根据该方法，通过镀铜，提供高纵横比的通孔。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009302501A

公开(公告)日：2009-12-24

申请号：JP2008260280

申请日：2008-10-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： HORAK DAVID VACLAV ,  SHOM PONOTH ,  YANG CHIH-CHAO

IPC: H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5226 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76849 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an interconnect structure having electromigration resistance enhanced by lining the inside of a lower portion of a via opening inside with a multi-layered liner.
SOLUTION: The multi-layered liner includes, from the patterned surface of a dielectric material outwards, a diffusion barrier, a multi-material layer and a metal-containing hard mask. The multi-material layer includes a first material layer comprised of residue from an underlying dielectric capping layer, and a second material layer comprised of residue from an underlying metallic capping layer. The present invention also provides a method of fabricating such an interconnect structure which includes the multi-layered liner within the lower portion of the via opening formed within a dielectric material.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种具有通过用多层衬垫衬里通孔内部的下部的内部而增强的电迁移阻力的互连结构。 解决方案：多层衬垫包括从介电材料的图案化表面向外的扩散阻挡层，多材料层和含金属的硬掩模。 多材料层包括由下面的电介质覆盖层的残留物构成的第一材料层和由下面的金属覆盖层的残留物构成的第二材料层。 本发明还提供一种制造这种互连结构的方法，其包括在介电材料内形成的通孔开口的下部内的多层衬垫。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：WO2009139962A3

公开(公告)日：2010-01-07

申请号：PCT/US2009038380

申请日：2009-03-26

Applicant: IBM ,  GIGNAC LYNNE M ,  HU CHAO-KUN ,  YANG CHIH-CHAO

Inventor： GIGNAC LYNNE M ,  HU CHAO-KUN ,  YANG CHIH-CHAO

IPC: H01L23/52 ,  H01L23/525 ,  H01L23/532

CPC classification number: H01L23/53295 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76888 ,  H01L23/5226 ,  H01L23/5256 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure is provided that includes an interconnect structure and a fuse structure located in different areas, yet within the same interconnect level. The interconnect structure has high electromigration resistance, while the fuse structure has a lower electromigration resistance as compared with the interconnect structure. The fuse structure includes a conductive material embedded within an interconnect dielectric in which the upper surface of the conductive material has a high concentration of oxygen present therein. A dielectric capping layer is located atop the dielectric material and the conductive material. The presence of the surface oxide layer at the interface between the conductive material and the dielectric capping layer degrades the adhesion between the conductive material and the dielectric capping layer. As such, when current is provided to the fuse structure electromigration of the conductive material occurs and over time an opening is formed in the conductive material blowing the fuse element.

Abstract translation: 提供了一种半导体结构，其包括互连结构和位于相同互连级别内的不同区域中的熔丝结构。 互连结构具有高的电迁移率，而与互连结构相比，熔丝结构具有较低的电迁移电阻。 熔丝结构包括嵌入在互连电介质内的导电材料，其中导电材料的上表面具有存在于其中的高浓度的氧。 电介质覆盖层位于电介质材料和导电材料的顶部。 在导电材料和电介质覆盖层之间的界面处的表面氧化物层的存在降低了导电材料和电介质覆盖层之间的粘合性。 因此，当电流提供给熔丝结构时，导电材料的电迁移发生，并且随着时间的推移，在引导熔丝元件的导电材料中形成开口。

公开(公告)号：WO2007044305A3

公开(公告)日：2007-12-13

申请号：PCT/US2006038475

申请日：2006-10-03

Applicant: IBM ,  YANG CHIH-CHAO ,  GAUDET SIMON ,  LAVOIE CHRISTIAN ,  PONOTH SHOM ,  SPOONER TERRY A

Inventor： YANG CHIH-CHAO ,  GAUDET SIMON ,  LAVOIE CHRISTIAN ,  PONOTH SHOM ,  SPOONER TERRY A

IPC: H01L23/58

CPC classification number: H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof, and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen/nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen/nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed.

Abstract translation: 提供了一种互连结构，该互连结构包括具有增强的导电材料（优选Cu）扩散性质的镀敷种子层，其消除了使用单独的扩散层和种子层的需要。 具体而言，本发明提供用于互连金属扩散增强的镀敷种子层内的氧/氮过渡区。 电镀种子层可以包括Ru，Ir或其合金，互连导电材料可以包括Cu，Al，AlCu，W，Ag，Au等等。 优选地，互连导电材料是Cu或AlCu。 更具体地说，本发明提供了包括夹在顶部和底部种子区之间的氧/氮过渡区的单种晶层。 电镀种子层内氧/氮过渡区的存在显着增强了电镀种子的扩散阻挡性。

公开(公告)号：WO2006113186A3

公开(公告)日：2008-07-24

申请号：PCT/US2006013179

申请日：2006-04-07

Applicant: IBM ,  YANG CHIH-CHAO ,  CLEVENGER LAWRENCE A ,  COWLEY ANDREW P ,  DALTON TIMOTHY J ,  YOON MEEYOUNG H

Inventor： YANG CHIH-CHAO ,  CLEVENGER LAWRENCE A ,  COWLEY ANDREW P ,  DALTON TIMOTHY J ,  YOON MEEYOUNG H

IPC: H01L21/4763

CPC classification number: H01L21/76849 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76831 ,  H01L21/76843 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A damascene wire and method of forming the wire. The method including: forming a mask layer on a top surface of a dielectric layer; forming an opening in the mask layer; forming a trench in the dielectric layer where the dielectric layer is not protected by the mask layer; recessing the sidewalls of the trench under the mask layer; forming a conformal conductive liner on all exposed surface of the trench and the mask layer; filling the trench with a core electrical conductor; removing portions of the conductive liner extending above the top surface of the dielectric layer and removing the mask layer; and forming a conductive cap on a top surface of the core conductor. The structure includes a core conductor clad in a conductive liner and a conductive capping layer in contact with the top surface of the core conductor that is not covered by the conductive liner.

Abstract translation: 一种镶嵌线及其形成方法。 该方法包括：在电介质层的顶表面上形成掩模层; 在掩模层中形成开口; 在电介质层中形成沟槽，其中电介质层不被掩模层保护; 使掩模层下方的沟槽的侧壁凹陷; 在沟槽和掩模层的所有暴露表面上形成共形导电衬垫; 用芯电导体填充沟槽; 去除在电介质层的顶表面上方延伸的导电衬垫的部分，并去除掩模层; 以及在所述芯导体的顶表面上形成导电帽。 该结构包括包覆在导电衬垫中的芯导体和与未被导电衬垫覆盖的芯导体的顶表面接触的导电覆盖层。

公开(公告)号：WO2007027813A3

公开(公告)日：2007-12-06

申请号：PCT/US2006033924

申请日：2006-08-30

Applicant: IBM ,  HSU LOUIS C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  RADENS CARL J ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

Inventor： HSU LOUIS C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  RADENS CARL J ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01P1/10

CPC classification number: H01H50/005 ,  H01H2050/007 ,  Y10T29/4902 ,  Y10T29/49105 ,  Y10T29/49147

Abstract: A MEM switch is described having a free moving element (140) within in micro-cavity (40), and guided by at least one inductive element. The switch consists of an upper inductive coil (170); an optional lower inductive coil (190), each having a metallic core (180,200) preferably made of permalloy; a micro-cavity (40); and a free-moving switching element (140) also made of magnetic material. Switching is achieved by passing a current through the upper coil, inducing a magnetic field in the coil element. The magnetic field attracts the free-moving magnetic element upwards, shorting two open wires (M_I M_r) and thus, closing the switch. When the current flow stops or is reversed, the free-moving magnetic element drops back by gravity to the bottom of the micro-cavity and the wires open. When gravity cannot be used, a lower coil becomes necessary to pull the free-moving switching element back and holding it at its original position.

Abstract translation: 描述了一种MEM开关，其具有在微腔（40）内的自由移动元件（140），并由至少一个电感元件引导。 开关由上部感应线圈（170）组成; 可选的下感应线圈（190），每个具有优选由坡莫合金制成的金属芯（180,200） 微腔（40）; 以及也由磁性材料制成的自由移动的开关元件（140）。 通过使电流通过上部线圈来实现切换，从而在线圈元件中产生磁场。 磁场向上吸引自由移动的磁性元件，使两根开放的导线（M_I M_r）短路，从而闭合开关。 当电流停止或反转时，自由移动的磁性元件通过重力返回到微腔的底部并且电线打开。 当不能使用重力时，需要下部线圈将自由移动的开关元件拉回并将其保持在其原始位置。

公开(公告)号：EP2567400A4

公开(公告)日：2017-12-27

申请号：EP11777742

申请日：2011-03-21

Applicant: IBM

Inventor： HORAK DAVID V ,  NOGAMI TAKESHI ,  PONOTH SHOM ,  YANG CHIH-CHAO

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76805 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Interconnect structures having self-aligned dielectric caps are provided. At least one metallization level is formed on a substrate. A dielectric cap is selectively deposited on the metallization level.