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    METHOD AND STRUCTURE FOR LOW RESISTIVE SOURCE AND DRAIN REGIONS IN A REPLACEMENT METAL GATE PROCESS FLOW
    3.
    发明申请
    METHOD AND STRUCTURE FOR LOW RESISTIVE SOURCE AND DRAIN REGIONS IN A REPLACEMENT METAL GATE PROCESS FLOW 审中-公开
    替代金属浇口工艺流程中低电阻源和漏区的方法和结构

    公开(公告)号：WO2013002902A3

    公开(公告)日：2013-04-25

    申请号：PCT/US2012037919

    申请日：2012-05-15

    Applicant: IBM ,  HARAN BALASUBRAMANIAN ,  CHENG KANGGUO ,  PONOTH SHOM ,  STANDAERT THEODORUS E ,  YAMASHITA TENKO

    Inventor： HARAN BALASUBRAMANIAN ,  CHENG KANGGUO ,  PONOTH SHOM ,  STANDAERT THEODORUS E ,  YAMASHITA TENKO

    IPC: H01L21/336 ,  H01L21/8238 ,  H01L29/78

    CPC classification number: H01L21/84 ,  H01L21/22 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

    Abstract: In one embodiment a method is provided that includes providing a structure including a semiconductor substrate (12) having at least one device region (14) located therein, and a doped semiconductor layer located on an upper surface of the semiconductor substrate in the at least one device region. After providing the structure, a sacrificial gate region (28) having a spacer (34) located on sidewalls thereof is formed on an upper surface of the doped semiconductor layer. A planarizing dielectric material (36) is then formed and the sacrificial gate region (28) is removed to form an opening (38) that exposes a portion of the doped semiconductor layer. The opening is extended to an upper surface of the semiconductor substrate (20) and then an anneal is performed that causes outdiffusion of dopant from remaining portions of the doped semiconductor layer forming a source region (40) and a drain region (42) in portions of the semiconductor substrate that are located beneath the remaining portions of the doped semiconductor layer. A high k gate dielectric (46) and a metal gate (48) are then formed into the extended opening.

    Abstract translation: 在一个实施例中，提供了一种方法，其包括提供包括具有位于其中的至少一个器件区域（14）的半导体衬底（12）的结构，以及位于所述至少一个中的所述半导体衬底的上表面上的掺杂半导体层 设备区域。 在提供结构之后，在掺杂半导体层的上表面上形成具有位于其侧壁上的间隔物（34）的牺牲栅极区域（28）。 然后形成平坦化电介质材料（36），去除牺牲栅极区域（28）以形成露出掺杂半导体层的一部分的开口（38）。 开口延伸到半导体衬底（20）的上表面，然后执行退火，其导致部分地形成源区（40）和漏区（42）的掺杂半导体层的剩余部分的扩散扩散 位于掺杂半导体层的剩余部分下方的半导体衬底。 然后，将高k栅极电介质（46）和金属栅极（48）形成为延伸的开口。

    PLATING SEED LAYER INCLUDING AN OXYGEN/NITROGEN TRANSITION REGION FOR BARRIER ENHANCEMENT
    4.
    发明申请
    PLATING SEED LAYER INCLUDING AN OXYGEN/NITROGEN TRANSITION REGION FOR BARRIER ENHANCEMENT 审中-公开
    包括氧/氮转换区在内的电镀层用于屏障增强

    公开(公告)号：WO2007044305A3

    公开(公告)日：2007-12-13

    申请号：PCT/US2006038475

    申请日：2006-10-03

    Applicant: IBM ,  YANG CHIH-CHAO ,  GAUDET SIMON ,  LAVOIE CHRISTIAN ,  PONOTH SHOM ,  SPOONER TERRY A

    Inventor： YANG CHIH-CHAO ,  GAUDET SIMON ,  LAVOIE CHRISTIAN ,  PONOTH SHOM ,  SPOONER TERRY A

    IPC: H01L23/58

    CPC classification number: H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof, and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen/nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen/nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed.

    Abstract translation: 提供了一种互连结构，该互连结构包括具有增强的导电材料（优选Cu）扩散性质的镀敷种子层，其消除了使用单独的扩散层和种子层的需要。 具体而言，本发明提供用于互连金属扩散增强的镀敷种子层内的氧/氮过渡区。 电镀种子层可以包括Ru，Ir或其合金，互连导电材料可以包括Cu，Al，AlCu，W，Ag，Au等等。 优选地，互连导电材料是Cu或AlCu。 更具体地说，本发明提供了包括夹在顶部和底部种子区之间的氧/氮过渡区的单种晶层。 电镀种子层内氧/氮过渡区的存在显着增强了电镀种子的扩散阻挡性。

    Low-profile local interconnect and method of making the same
    6.
    发明专利
    Low-profile local interconnect and method of making the same 未知

    公开(公告)号：GB2507011B

    公开(公告)日：2015-06-10

    申请号：GB201401202

    申请日：2012-03-12

    Applicant: IBM

    Inventor： PONOTH SHOM ,  HORAK DAVID V ,  KOBURGER CHARLES W ,  YANG CHIH-CHAO

    IPC: H01L21/8234

    Abstract: Embodiments of the present invention provide a structure. The structure includes a plurality of field-effect-transistors having gate stacks formed on top of a semiconductor substrate, the gate stacks having spacers formed at sidewalls thereof; and one or more conductive contacts formed directly on top of the semiconductor substrate and interconnecting at least one source/drain of one of the plurality of field-effect-transistors to at least one source/drain of another one of the plurality of field-effect-transistors, wherein the one or more conductive contacts is part of a low-profile local interconnect that has a height lower than a height of the gate stacks.

    Integrierte Schaltungen und Verfahren zum Herstellen von integrierten Schaltungen mit Metall-Gate-Elektroden
    8.
    发明专利
    Integrierte Schaltungen und Verfahren zum Herstellen von integrierten Schaltungen mit Metall-Gate-Elektroden 未知

    公开(公告)号：DE102013220852B4

    公开(公告)日：2015-12-24

    申请号：DE102013220852

    申请日：2013-10-15

    Applicant: GLOBALFOUNDRIES INC ,  IBM

    Inventor： XIE RUILONG ,  PARK CHANRO ,  PONOTH SHOM

    IPC: H01L21/336 ,  H01L21/822 ,  H01L29/423 ,  H01L29/78

    Abstract: Verfahren zum Herstellen einer integrierten Schaltung, wobei das Verfahren umfasst: Vorsehen eines Opfer-Gate-Aufbaus über einem Halbleitersubstrat, wobei der Opfer-Gate-Aufbau zwei Abstandshalter und ein Opfer-Gate-Material zwischen den zwei Abstandshaltern enthält, Vertiefen eines Teils des Opfer-Gate-Materials zwischen den zwei Abstandshaltern, Ätzen von oberen Bereichen der zwei Abstandshalter, wobei das Opfer-Gate-Material als eine Maske verwendet wird, Entfernen eines verbleibenden Teils des Opfer-Gate-Materials und Freilegen von unteren Bereichen der zwei Abstandshalter, Deponieren eines ersten Metalls zwischen den zwei Abstandshaltern, Entfernen des ersten Metalls zwischen den oberen Bereichen der zwei Abstandshalter, und Deponieren eines zweiten Metalls zwischen den oberen Bereichen der zwei Abstandshalter.

    Strukturen flacher Grabenisolierungen
    9.
    发明专利
    Strukturen flacher Grabenisolierungen 未知

    公开(公告)号：DE112013002186T5

    公开(公告)日：2015-01-15

    申请号：DE112013002186

    申请日：2013-03-13

    Applicant: IBM

    Inventor： DORIS BRUCE B ,  CHENG KANGGUO ,  HARAN BALASUBRAMANIAN S ,  KHAKIFIROOZ ALI ,  KULKARNI PRANITA ,  KUMAR ARVIND ,  PONOTH SHOM

    IPC: H01L21/762

    Abstract: Es werden Strukturen flacher Grabenisolierungen zur Verwendung mit UTBB(Ultra-Thin Body and Buried Oxide)-Halbleitersubstraten bereitgestellt, welche verhindern, dass Defektmechanismen wie z. B. die Bildung elektrischer Kurzschlüsse zwischen frei liegenden Abschnitten von Siliciumschichten an den Seitenwänden eines flachen Grabens eines UTBB-Substrats in Fällen auftreten, wenn anschließend ein Grabenfüllmaterial des flachen Grabens weggeätzt und bis unter eine obere Fläche des UTBB-Substrats ausgespart wird.

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