公开(公告)号：AU2002352993A1

公开(公告)日：2003-07-09

申请号：AU2002352993

申请日：2002-11-26

Applicant: IBM

Inventor： YU ROY ,  PRASAD CHANDRIKA ,  NARAYAN CHANDRASEKHAR ,  POGGE BERNHARD H

IPC: H01L23/12 ,  H01L21/68 ,  H01L21/768 ,  H01L23/48 ,  H01L23/485 ,  H01L23/525 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  H01L21/8234

Abstract: A metallized feature is formed in the top surface of a substrate, and a handling plate is attached to the substrate. The substrate is then thinned at the bottom surface thereof to expose the bottom of the feature, to form a conducting through-via. The substrate may comprise a chip having a device (e.g. DRAM) fabricated therein. The process therefore permits vertical integration with a second chip (e.g. a PE chip). The plate may be a wafer attached to the substrate using a vertical stud/via interconnection. The substrate and plate may each have devices fabricated therein, so that the process provides vertical wafer-level integration of the devices.