公开(公告)号：CA1078466A

公开(公告)日：1980-05-27

申请号：CA272257

申请日：1977-02-21

Applicant: IBM

Inventor： ZAPPE HANS H

IPC: H03K19/195

Abstract: AN ELECTRONICALLY ALTERABLE NON-LATCHING JOSEPHSON AND, OR, NAND, NOR LOGIC CIRCUIT An electronically alterable logic circuit is disclosed which provides different logical outputs which are a function of control signals applied to the circuit. More specifically, a non-latching Josephson junction circuit is provided which is capable of providing true and complementary outputs at a pair of output terminals when at least one pair of a plurality of pairs of fixed biases are applied to a plurality of serially arranged Josephson junction devices. The Josephson devices are arranged so that a true output can be obtained from an output circuit which shunts a pair of Josephson devices while the complement of the true output can be obtained at an output circuit which shunts an appropriately biased Josephson junction which is disposed in series with the above mentioned pair of Josephson junctions. The complementary output is achieved by utilizing a portion of the output circuit, which shunts the pair of Josephson junctions as a control line for the single Josephson junction in series with the pair of Josephson junctions. The current through the control line portion, when present, opposes a bias current setting up a situation such that when current flows in the output representative of a true output, no current flows in the output representative of a complementary signal and vice versa. In addition to achieving true and complementary outputs which can be characterized as AND, NAND, OR and NOR outputs, it has been recognized that these same outputs can be attained at the complementary output by simply applying binary combinations of biases to the two bias lines associated with the logic circuit. In other words, if predetermined biases are applied, the input signals can, for example, be AND'ed while, for another set of biases for the same input signals, the input signals can be OR'd. Thus, for one period of time with a given set of biases, the circuit disclosed is capable of applying one logic function to the input signals while, in a second time period, the same circuit, by simply changing the biases, is capable of applying a different logic function to the same or different input signals. To the extent that a large number of such circuits is utilized in a data processor, the specific function of each circuit can be programmed from time period to time period so that the same circuitry can be configured in a different way and indeed appear as if an entirely different machine were available. The ability to electronically alter the logic function of a circuit has applications in the data secrecy and data scrambling areas.

公开(公告)号：CA1075827A

公开(公告)日：1980-04-15

申请号：CA272258

申请日：1977-02-21

Applicant: IBM

Inventor： KIRCHER CHARLES J ,  ZAPPE HANS H

IPC: H05K3/46 ,  H01L21/3063 ,  H01L21/316 ,  H01L21/3205 ,  H01L23/522 ,  H01L39/24 ,  H05K1/04 ,  H05K3/00

Abstract: ABOVE AND BELOW GROUND PLANE WIRING A fabrication method for integrated circuits is disclosed wherein a structure is formed on one side of a supporting substrate which provides a ground plane with "X" wiring on one side and "Y" wiring on the other side thereof. The method includes a number of alternative initial planarization steps which permits the resulting device to be substantially planar, thereby allowing it to be used as a substrate for preparation of high density integrated circuits. A first planarization step includes the deposition of a niobium thin film on a doped silicon substrate; the delineation of the desired niobium "X" wiring pattern using well-known photolithographic and etching techniques, leaving the photoresist in place to protect the niobium; the anodization of exposed silicon substrate portions to form silicon dioxide surrounding the niobium to a higher level then the niobium; and the removal of the photoresist.

公开(公告)号：FR2396421A1

公开(公告)日：1979-01-26

申请号：FR7805798

申请日：1978-02-23

Applicant: IBM

Inventor： ZAPPE HANS H

IPC: H01L39/22 ,  H03K17/92 ,  H03K19/195

Abstract: JOSEPHSON INTERFEROMETER STRUCTURE WHICH SUPPRESSES RESONANCES Josephson interferometers contain inductive, capacitive and resistive components, and, as a result, such devices are subject to the presence of relatively high amplitude resonances similar to those found in in-line gates. Interferometer structures exhibit the same resonant behavior as long tunnel junctions, except that there exist only as many discrete resonance voltages as meshes in the interferometer device. Hence, a two-junction interferometer has one resonance as compared to two resonances in a three-junction device. In the I-V characteristic of a Josephson tunneling device such as an interferometer, such resonances appear as current steps which must be taken into account in the design of Josephson switching circuits primarily to avoid the situation where the load line of an external load intersects a resonance peak. Where the load line and the resonance peak intersect, because such an intersection is stable, the device is prevented from switching to the full voltage desired. Such resonances can be effectively suppressed in interferometers by providing a resistance which is in parallel with the main inductance of the interferometer. In a two-junction interferometer, the resistance is effectively connected between the base electrode metallizations which are utilized to form one of the electrodes of each of the pair of electrodes required for each interferometer junction. To the extent that more than two junctions are utilized, the resonance suppressing resistor is connected between pairs of junctions and across the main inductances which interconnect the junctions. The structure of a two-junction interferometer with its resonance-suppressing resistor, RSR, is shown as well as the schematics of a multiple junction interferometer which clearly indicates how such structures may be fabricated.

公开(公告)号：FR2366748A1

公开(公告)日：1978-04-28

申请号：FR7704311

申请日：1977-02-11

Applicant: IBM

Inventor： ZAPPE HANS H

IPC: H03K19/195

Abstract: An electronically alterable logic circuit is disclosed which provides different logical outputs which are a function of control signals applied to the circuit. More specifically, a non-latching Josephson junction circuit is provided which is capable of providing true and complementary outputs at a pair of output terminals when at least one pair of a plurality of pairs of fixed biases are applied to a plurality of serially arranged Josephson junction devices. The Josephson devices are arranged so that a true output can be obtained from an output circuit which shunts a pair of Josephson devices while the complement of the true output can be obtained at an output circuit which shunts an appropriately biased Josephson junction which is disposed in series with the above mentioned pair of Josephson junctions. The complementary output is achieved by utilizing a portion of the output circuit which shunts the pair of Josephson junctions as a control line for the single Josephson junction in series with the pair of Josephson junctions. The current through the control line portion, when present, opposes a bias current setting up a situation such that when current flows in the output representative of a true output, no current flows in the output representative of a complementary signal and vice versa. In addition to achieving true and complementary outputs which can be characterized as AND, NAND, OR and NOR outputs, it has been recognized that these same outputs can be attained at the complementary output by simply applying binary combinations of biases to the two bias lines associated with the logic circuit.

公开(公告)号：CA1044768A

公开(公告)日：1978-12-19

申请号：CA254966

申请日：1976-06-16

Applicant: IBM

Inventor： ZAPPE HANS H

IPC: H03K19/195 ,  H01L39/22 ,  H03K17/92

Abstract: QUANTUM INTERFERENCE JOSEPHSON LOGIC DEVICES A quantum interference Josephson junction logic device is disclosed which comprises three or more junctions connected in parallel which are capable of carrying Josephson current and includes means integral with at least one of the junctions for carrying a larger maximum Josephson current than the remaining junctions. The spacing between the lobes of the threshold curve is increased over that of a two junction interferometer resulting in an increased operating region in which logic circuits switch to the voltage state. Good current gain with large lobe separation may be obtained if the two outer junctions having a zero field threshold current, I0, are connected via an inductance, L, to the center junction with a maximum Josephson current, 210. Apart from the gain enhancement due to increased current in at least one of the junctions and that due to the combination of increased current in at least one of the junctions and the symmetrical dual feed, increased gain and operating range can be achieved using the symmetrical dual feed in combination with interferometer arrangements where the maximum Josephson current in all the junctions thereof is the same.

公开(公告)号：CA1038495A

公开(公告)日：1978-09-12

申请号：CA291578

申请日：1977-11-23

Applicant: IBM

Inventor： ZAPPE HANS H

IPC: G11C11/44

Abstract: DAMPED JOSEPHSON JUNCTION MEMORY CELL A memory cell comprising at least one Josephson junction is properly damped for effective operation by inductively coupling a resistive loop to the memory cell. The resistive loop may be located in the vicinity of the vertical projection of the memory cell so as to not affect the packing of a plurality of memory cells.

公开(公告)号：FR2357069A1

公开(公告)日：1978-01-27

申请号：FR7704312

申请日：1977-02-11

Applicant: IBM

Inventor： KIRCHER CHARLES J ,  ZAPPE HANS H

IPC: H01L21/3063 ,  H01L21/316 ,  H05K3/46 ,  H01L21/3205 ,  H01L23/522 ,  H01L39/24 ,  H01L21/88

Abstract: A fabrication method for integrated circuits is disclosed wherein a structure is formed on one side of a supporting substrate which provides a ground plane with "X" wiring on one side and "Y" wiring on the other side thereof. The method includes a number of alternative initial planarization steps which permits the resulting device to be substantially planar, thereby allowing it to be used as a substrate for preparation of high density integrated circuits. A first planarization step includes the deposition of a niobium thin film on a doped silicon substrate; the delineation of the desired niobium "X" wiring pattern using well-known photolithographic and etching techniques, leaving the photoresist in place to protect the niobium; the anodization of exposed silicon substrate portions to form silicon dioxide surrounding the niobium to a higher level than the niobium; and the removal of the photoresist.

公开(公告)号：AU8143475A

公开(公告)日：1976-11-25

申请号：AU8143475

申请日：1975-05-22

Applicant: IBM

Inventor： ZAPPE HANS H

IPC: G11C11/14 ,  G11C11/44 ,  H01L39/22

Abstract: An information storage device which stores a single flux quantum without bias is disclosed. The device includes a single Josephson tunneling device made from two superconductive materials spaced apart by an insulator wherein a Josephson current density profile J1(x) defined by + INFINITY J1(x) =J1(x,y)dy - INFINITY IS CHARACTERIZED SUCH THAT THE PROFILE HAS A LARGER MAGNITUDE AT THE BOUNDARY PORTIONS OF SAID DEVICE THAN AT THE CENTER. The current density profile is controlled by adjusting either the oxide thicknesses, the work function of the superconductors or by changing the shape of the junction from its usual rectangular cross-section.