公开(公告)号：CA1142264A

公开(公告)日：1983-03-01

申请号：CA365924

申请日：1980-12-02

Applicant: IBM

Inventor： AMES IRVING ,  ANACKER WILHELM ,  GREBE KURT R ,  KIRCHER CHARLES J

IPC: H01L27/18 ,  H01L23/485 ,  H01L23/532 ,  H01L39/02 ,  H01L39/22

Abstract: CONTACT TECHNIQUE FOR ELECTRICAL CIRCUITRY . In electrical circuitry, and particularly superconducting circuitry including Josephson tunnelling devices, it is often necessary to provide solder contacts to electrical lines, where the electrical lines would be destroyed if there were interdiffusion between the lines and the solder. To avoid this problem, a laterally extending metallic layer is used as a diffusion barrier between the solder land and the electrical line which can be a superconducting line. The diffusion barrier is comprised of a refractory metal which has a first portion electrically contacting the solder land and a second, laterally displaced portion electrically contacting the electrical line. An insulating protective layer on the diffusion barrier layer separates the solder land and the electrical line. In a specific embodiment, the superconducting electrical line is comprised of an alloy of lead while the diffusion barrier is comprised of niobium, and the solder alloy is a low melting point alloy, typically comprised of indium, bismuth,

公开(公告)号：CA1075827A

公开(公告)日：1980-04-15

申请号：CA272258

申请日：1977-02-21

Applicant: IBM

Inventor： KIRCHER CHARLES J ,  ZAPPE HANS H

IPC: H05K3/46 ,  H01L21/3063 ,  H01L21/316 ,  H01L21/3205 ,  H01L23/522 ,  H01L39/24 ,  H05K1/04 ,  H05K3/00

Abstract: ABOVE AND BELOW GROUND PLANE WIRING A fabrication method for integrated circuits is disclosed wherein a structure is formed on one side of a supporting substrate which provides a ground plane with "X" wiring on one side and "Y" wiring on the other side thereof. The method includes a number of alternative initial planarization steps which permits the resulting device to be substantially planar, thereby allowing it to be used as a substrate for preparation of high density integrated circuits. A first planarization step includes the deposition of a niobium thin film on a doped silicon substrate; the delineation of the desired niobium "X" wiring pattern using well-known photolithographic and etching techniques, leaving the photoresist in place to protect the niobium; the anodization of exposed silicon substrate portions to form silicon dioxide surrounding the niobium to a higher level then the niobium; and the removal of the photoresist.

公开(公告)号：CA1143864A

公开(公告)日：1983-03-29

申请号：CA361868

申请日：1980-09-26

Applicant: IBM

Inventor： KIRCHER CHARLES J ,  HUANG HUNG-CHANG W ,  MURAKAMI MASANORI

IPC: H01L39/22 ,  H01L39/24

Abstract: JOSEPHSON DEVICES OF IMPROVED THERMAL CYCLABILITY AND METHOD Thin film electrodes particularly suited for Josephson devices of improved thermal cyclability are prepared by depositing thin films of superconductive metal and an intermetallic compound former on a substrate held at a temperature below about 100.degree.K and at a pressure below about 1 x 10-7 Torr so that intermetallic compound formation occurs at the grain boundaries of the metal to inhibit grain growth. The thin film electrodes are characterized by median grain size

公开(公告)号：FR2357069A1

公开(公告)日：1978-01-27

申请号：FR7704312

申请日：1977-02-11

Applicant: IBM

Inventor： KIRCHER CHARLES J ,  ZAPPE HANS H

IPC: H01L21/3063 ,  H01L21/316 ,  H05K3/46 ,  H01L21/3205 ,  H01L23/522 ,  H01L39/24 ,  H01L21/88

Abstract: A fabrication method for integrated circuits is disclosed wherein a structure is formed on one side of a supporting substrate which provides a ground plane with "X" wiring on one side and "Y" wiring on the other side thereof. The method includes a number of alternative initial planarization steps which permits the resulting device to be substantially planar, thereby allowing it to be used as a substrate for preparation of high density integrated circuits. A first planarization step includes the deposition of a niobium thin film on a doped silicon substrate; the delineation of the desired niobium "X" wiring pattern using well-known photolithographic and etching techniques, leaving the photoresist in place to protect the niobium; the anodization of exposed silicon substrate portions to form silicon dioxide surrounding the niobium to a higher level than the niobium; and the removal of the photoresist.