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    Vertical metal-insulator-metal (mim) capacitor using gate stack, gate spacer and contact via
    13.
    发明专利
    Vertical metal-insulator-metal (mim) capacitor using gate stack, gate spacer and contact via 审中-公开
    垂直金属绝缘子金属（MIM）电容器使用盖板，隔板和接触器

    公开(公告)号：JP2010157704A

    公开(公告)日：2010-07-15

    申请号：JP2009271765

    申请日：2009-11-30

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： GAMBINO JEFFREY P ,  PETRARCA KEVIN S ,  FAROOQ MUKTA G ,  RAMACHANDRA DEIBAKARUNI

    IPC: H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/866

    CPC classification number: H01L28/60 ,  H01L21/76897 ,  H01L23/485 ,  H01L27/0629 ,  H01L27/0805 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide a metal-insulator-metal capacitor having improved manufacturing possibility, and to provide a method for fabricating the same. SOLUTION: A semiconductor structure including the vertical metal-insulator-metal capacitor, and a method for fabricating the semiconductor structure including the vertical metal-insulator-metal capacitor, each use structural components from a dummy metal oxide semiconductor field effect transistor located and formed over an isolation region located over a semiconductor substrate. The dummy metal oxide field effect transistor may be formed simultaneously with a metal oxide semiconductor field effect transistor located over a semiconductor substrate that includes the isolation region. The metal-insulator-metal capacitor uses a gate as a capacitor plate, a uniform thickness gate spacer as a gate dielectric and a contact via as another capacitor plate. The uniform thickness gate spacer may include a conductor layer for enhanced capacitance. A mirrored metal-insulator-metal capacitor structure that uses a single contact via may also be used for enhanced capacitance. COPYRIGHT: (C)2010,JPO&INPIT

    Abstract translation: 要解决的问题：提供具有改进的制造可能性的金属 - 绝缘体 - 金属电容器，并提供其制造方法。 解决方案：包括垂直金属 - 绝缘体 - 金属电容器的半导体结构以及包括垂直金属 - 绝缘体 - 金属电容器的半导体结构的制造方法，每个都使用来自虚设金属氧化物半导体场效应晶体管的结构部件 并且形成在位于半导体衬底上方的隔离区域上。 虚拟金属氧化物场效应晶体管可以与位于包括隔离区域的半导体衬底之上的金属氧化物半导体场效应晶体管同时形成。 金属 - 绝缘体 - 金属电容器使用栅极作为电容器板，均匀厚度的栅极间隔物作为栅极电介质和作为另一个电容器板的接触通孔。 均匀厚度的栅极间隔物可以包括用于增强电容的导体层。 使用单个接触通孔的镜像金属 - 绝缘体 - 金属电容器结构也可用于增强电容。 版权所有（C）2010，JPO＆INPIT

    LEAKAGE MEASUREMENT OF THROUGH SILICON VIAS
    16.
    发明申请
    LEAKAGE MEASUREMENT OF THROUGH SILICON VIAS 审中-公开
    通过硅胶渗漏测量

    公开(公告)号：WO2013040285A3

    公开(公告)日：2013-05-10

    申请号：PCT/US2012055276

    申请日：2012-09-14

    Applicant: IBM ,  BHOOVARAGHAN BHAVANA ,  FAROOQ MUKTA G ,  KINSER EMILY ,  SAROOP SUDESH

    Inventor： BHOOVARAGHAN BHAVANA ,  FAROOQ MUKTA G ,  KINSER EMILY ,  SAROOP SUDESH

    IPC: H01L21/66 ,  H01L21/28 ,  H01L21/768

    CPC classification number: H01L22/34 ,  H01L23/481 ,  H01L23/58 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A leakage measurement structure for through substrate vias which includes a semiconductor substrate; a plurality of through substrate vias in the semiconductor substrate extending substantially through the semiconductor substrate; and a leakage measurement structure located in the semiconductor substrate. The leakage measurement structure includes a plurality of substrate contacts extending into the semiconductor substrate; a plurality of sensing circuits connected to the plurality of through substrate vias and to the plurality of the substrate contacts, the plurality of sensing circuits providing a plurality of outputs indicative of current leakage from the plurality of through substrate vias; a built-in self test (BIST) engine to step through testing of the plurality of through substrate vias; and a memory coupled to the BIST engine to receive the outputs from the plurality of sensing circuits. Also included is a method of testing a semiconductor substrate.

    Abstract translation: 一种用于通过衬底通孔的泄漏测量结构，其包括半导体衬底; 半导体衬底中的多个穿过衬底通孔，其基本上延伸穿过半导体衬底; 以及位于半导体衬底中的泄漏测量结构。 泄漏测量结构包括延伸到半导体衬底中的多个衬底触点; 多个感测电路，连接到多个通过衬底通孔和多个衬底触点，所述多个感测电路提供指示来自多个通过衬底通孔的电流泄漏的多个输出; 一个内置的自检（BIST）引擎，逐步测试多个通过基板通孔; 以及耦合到BIST引擎以接收来自多个感测电路的输出的存储器。 还包括测试半导体衬底的方法。

    COAXIAL THROUGH-SILICON VIA
    18.
    发明申请
    COAXIAL THROUGH-SILICON VIA 审中-公开
    同轴通过硅

    公开(公告)号：WO2011056374A3

    公开(公告)日：2011-07-28

    申请号：PCT/US2010052594

    申请日：2010-10-14

    Applicant: IBM ,  VOLANT RICHARD P ,  FAROOQ MUKTA G ,  FINDEIS PAUL F ,  PETRARCA KEVIN S

    Inventor： VOLANT RICHARD P ,  FAROOQ MUKTA G ,  FINDEIS PAUL F ,  PETRARCA KEVIN S

    IPC: H01L21/768

    CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A through-silicon via (TSV) structure forming a unique coaxial or triaxial interconnect within the silicon substrate 40. The TSV structure is provided with two or more independent electrical conductors 50, 60 insulated from another and from the substrate. The electrical conductors can be connected to different voltages or ground, making it possible to operate the TSV structure as a coaxial or triaxial device. Multiple layers using various insulator materials can be used as insulator, wherein the layers are selected based on dielectric properties, fill properties, interfacial adhesion, CTE match, and the like. The TSV structure overcomes defects in the outer insulation layer that may lead to leakage. A method of fabricating such a TSV structure is also described.

    Abstract translation: 在硅衬底40内形成独特的同轴或三轴互连的贯通硅通孔（TSV）结构.TSV结构设置有两个或更多个独立的电导体50,60，与其彼此绝缘并与衬底绝缘。 电导体可以连接到不同的电压或接地，使得可以将TSV结构作为同轴或三轴装置进行操作。 使用各种绝缘材料的多层可用作绝缘体，其中根据介电性能，填充性能，界面粘合性，CTE匹配等来选择层。 TSV结构克服了外绝缘层中可能导致泄漏的缺陷。 还描述了制造这种TSV结构的方法。

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