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    ETCHING AGENT COMPOSITION
    11.
    发明专利
    ETCHING AGENT COMPOSITION 失效

    公开(公告)号：JPH11243085A

    公开(公告)日：1999-09-07

    申请号：JP32532998

    申请日：1998-11-16

    Applicant: IBM ,  SIEMENS AG

    Inventor： RATH DAVID LEE ,  RAMACHANDRAN RAVIKUMAR

    IPC: C09D9/00 ,  C09K13/08 ,  C11D3/39 ,  C11D7/08 ,  C11D11/00 ,  C23F1/16 ,  H01L21/302 ,  H01L21/304 ,  H01L21/308 ,  H01L21/311

    Abstract: PROBLEM TO BE SOLVED: To effectively eliminate polymer and via residues from a substrate or a conductive material by setting etching agent composition to solution containing sulfuric acid of specific wt.%, hydrogen peroxide of specific wt.% or ozone of specific ppm, and hydrofluoric acid of specific ppm. SOLUTION: Etching agent composition is set to solution containing sulfuric acid of approximately 0.01-approximately 15 wt.%, hydrogen peroxide of approximately 0.01approximately 20 wt.%, hydrofluoric acid of approximately 0.1-approximately 100 ppm or ozone of approximately 1-approximately 30 ppm, and residues being substantially equal to water. The etching agent composition is made by mixing sulfuric acid solution such as solution of 98 wt.%, hydrogen peroxide solution such as solution of 30 wt.%, and hydrofluoric acid solution such as solution of 49 wt.% together, and by adding water where the sulfuric acid, hydrogen peroxide, and hydrofluoric acid of desired percents are given.

    APPARATUS AND METHOD OF IMPROVED CLEANING AND DRYING SEMICONDUCTOR WAFER
    12.
    发明专利
    APPARATUS AND METHOD OF IMPROVED CLEANING AND DRYING SEMICONDUCTOR WAFER 失效

    公开(公告)号：JPH11162913A

    公开(公告)日：1999-06-18

    申请号：JP27613498

    申请日：1998-09-29

    Applicant: SIEMENS AG ,  IBM

    Inventor： AKATSU HIROYUKI ,  RAMACHANDRAN RAVIKUMAR

    IPC: H01L21/304 ,  H01L21/00

    Abstract: PROBLEM TO BE SOLVED: To clean and dry a semiconductor wafer by utilizing Marangoni effect, in which a liquid flow goes away from the wafer. SOLUTION: A housing 12, made up of upper and lower parts stores at least one wafer (W) during cleaning and drying. In a cleaning and drying apparatus, a movable supporting member 16 in the housing 12, a feeding means 40 for feeding organic vapor to the housing 12, and a feeding means 30 for feeding a wafer cleaning solution 60 to the housing 12 are provided. The wafer cleaning solution 60 is cooled sufficiently below an atmospheric temperature.

    COMPOSITION AND METHOD FOR REDUCING DISHING ON SURFACE OF WIDE PATTERNED BURIED METAL
    13.
    发明专利
    COMPOSITION AND METHOD FOR REDUCING DISHING ON SURFACE OF WIDE PATTERNED BURIED METAL 失效

    公开(公告)号：JP2000169831A

    公开(公告)日：2000-06-20

    申请号：JP26049599

    申请日：1999-09-14

    Applicant: SIEMENS AG ,  IBM

    Inventor： LIN CHENTING ,  WANG JIUN-FANG ,  JAMIN FEN FEN ,  RAMACHANDRAN RAVIKUMAR

    IPC: B24B37/00 ,  C09G1/02 ,  C09K3/14 ,  H01L21/302 ,  H01L21/304 ,  H01L21/321 ,  H01L21/768

    Abstract: PROBLEM TO BE SOLVED: To obtain the subject composition capable of reducing the dishing on the surface of a wide patterned buried metal in a conductor, when an article having the patterned metal in the conductor is subjected to chemical and mechanical polishing treatments by adding a viscosity-increasing agent to a slurry containing a polishing agent in stead of a part of deionized water in the slurry. SOLUTION: A viscosity-improving agent is added in stead of a part of deionized water in a slurry containing a polishing material. The viscosity- improving agent is preferably glycerol and is replaced with 0.1-50 vol.% of the deionized water. The polishing material is preferably alumina. The composition preferably has a viscosity of 3.4-12 cps. When a conductor to be processed is treated, it is preferable that the surface of the conductor is exposed to the composition.

    SELF-ALIGNED CONTACTS FOR HIGH K/METAL GATE PROCESS FLOW
    16.
    发明申请
    SELF-ALIGNED CONTACTS FOR HIGH K/METAL GATE PROCESS FLOW 审中-公开
    高K /金属闸门工艺流程的自对准接触

    公开(公告)号：WO2012106056A3

    公开(公告)日：2012-10-18

    申请号：PCT/US2012020020

    申请日：2012-01-03

    Applicant: IBM ,  RAMACHANDRAN RAVIKUMAR ,  DIVAKARUNI RAMACHANDRA ,  LI YING

    Inventor： RAMACHANDRAN RAVIKUMAR ,  DIVAKARUNI RAMACHANDRA ,  LI YING

    IPC: H01L29/78 ,  H01L21/28 ,  H01L21/336

    CPC classification number: H01L29/401 ,  H01L21/76895 ,  H01L21/76897 ,  H01L29/49 ,  H01L29/4983 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/6656

    Abstract: A semiconductor structure is provided that includes a semiconductor substrate 12 having a plurality of gate stacks 14' located on a surface of the semiconductor substrate. Each gate stack includes, from bottom to top, a high k gate dielectric layer 42, a work function metal layer 44 and a conductive metal 46. A spacer 22 is located on sidewalls of each gate stack and a self- aligned dielectric liner 30 is present on an upper surface of each spacer. A bottom surface of each self-aligned dielectric liner 30 is present on an upper surface of a semiconductor metal alloy 28. A contact metal 34 is located between neighboring gate stacks and is separated from each gate stack by the self-aligned dielectric liner 30. The structure also includes another contact metal 60 having a portion that is located on and in direct contact with an upper surface of the contact metal and another portion that is located on and in direct contact with the conductive metal of one of the gate stacks. Methods of forming the semiconductor structure using a replacement gate and a non-replacement gate scheme are also disclosed.

    Abstract translation: 提供半导体结构，其包括具有位于半导体衬底的表面上的多个栅极叠层14'的半导体衬底12。 每个栅极堆叠从底部到顶部包括高k栅极电介质层42，功函数金属层44和导电金属46.间隔物22位于每个栅极堆叠的侧壁上，并且自对准电介质衬垫30是 存在于每个间隔件的上表面上。 每个自对准电介质衬垫30的底表面存在于半导体金属合金28的上表面上。接触金属34位于相邻的栅极叠层之间并且通过自对准电介质衬垫30与每个栅极叠层分开。 该结构还包括另一接触金属60，其具有位于接触金属的上表面上并与其直接接触的部分以及位于栅叠层中的一个的导电金属上并与其直接接触的另一部分。 还公开了使用替代栅极和非替代栅极方案形成半导体结构的方法。

    СПОСОБ ПОЛУЧЕНИЯ МНОГОСЛОЙНОЙ ЗАТВОРНОЙ СТРУКТУРЫ И ЕЕ УСТРОЙСТВО
    19.
    发明专利
    СПОСОБ ПОЛУЧЕНИЯ МНОГОСЛОЙНОЙ ЗАТВОРНОЙ СТРУКТУРЫ И ЕЕ УСТРОЙСТВО 未知

    公开(公告)号：RU2498446C2

    公开(公告)日：2013-11-10

    申请号：RU2011132473

    申请日：2009-11-19

    Applicant: IBM ,  FRISKEJL SEMIKONDAKTOR INK

    Inventor： RAMACHANDRAN RAVIKUMAR ,  JAN KHUNVEHN ,  MOUMEN NAIM ,  SHEHFFER DZHEJMS KENION ,  KRISHNAN SIDDART A ,  VON KEJT KVON KHON ,  KVON UNOKH ,  BELJANSKI MAJKL P ,  UAJZ RICHARD

    IPC: H01L21/3205 ,  B82B3/00

    Abstract: Изобретениеотноситсяк получениюмногослойнойзатворнойструктурыдляполевоготранзистора. Сущностьизобретения: способполучениямногослойнойзатворнойструктурыдляполевыхтранзистороввключаетформированиеметаллсодержащегослоянепосредственнонапервомслоенитридатитана TiN, покрывающемобластиполупроводниковойподложки, предназначенныедляпервогои второготиповполевыхтранзисторов, формированиезащитногослояпутемнанесениявторого TiN-слояповерхметаллсодержащегослоя, формированиерисунканавтором TiN-слоеи металлсодержащемслоедляпокрытиятолькопервойчастипервого TiN-слоя, покрывающейобласть, предназначеннуюдляполевыхтранзисторовпервоготипа, вытравливаниевторойчастипервого TiN-слоя, оставшейсяоткрытойприформированиирисунка, втовремякакперваячастьпервого TiN-слояостаетсязащищеннойоттравлениязасчетеезакрытияпоменьшеймеречастьютолщиныметаллсодержащегослоя, накоторомсформированрисунок, иформированиетретьего TiN-слоя, покрывающегообластьполупроводниковойподложки, предназначеннуюдлявтороготипаполевыхтранзисторов. Изобретениеобеспечиваетусовершенствованиетехнологииполучениямногослойнойзатворнойструктуры. 3 н. и 24 з.п. ф-лы, 9 ил.

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