公开(公告)号：DE10360537A1

公开(公告)日：2004-08-05

申请号：DE10360537

申请日：2003-12-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KNORR ANDREAS ,  WISE MICHAEL

IPC: H01L21/762 ,  H01L27/108

Abstract: A method of forming deep isolation trenches in the fabrication of ICs is disclosed. The substrate is prepared with deep isolation trenches. The isolation trenches are partially filled with a first dielectric material. An etch mask layer is deposited on the substrate and used to remove excess first dielectric material on the surface of the substrate. The isolation trenches are then completely filled with a second dielectric material. Excess second dielectric material is then removed from the surface of the substrate.

公开(公告)号：DE10354717A1

公开(公告)日：2004-07-15

申请号：DE10354717

申请日：2003-11-22

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  ECONOMIKOS LAERTIS ,  KNORR ANDREAS ,  WISE MICHAEL L

IPC: H01L21/304 ,  H01L21/302 ,  H01L21/3105 ,  H01L21/461 ,  H01L21/768 ,  H01L21/8242

Abstract: CMP of integrated circuits containing DRAM arrays with trench capacitors fill the trenches with oxide, resulting in a an array of oxide structures that is dense compared with the concentration in the surrounding support structures and therefore has a higher loading. A conformal layer is deposited over the wafer, increasing the loading in the array, but filling in spaces between active areas. A blanket etch removes material in both the array and the supports. A block etch balances the amount of material in the array and the supports. A supplementary oxide deposition in the array fills spaces between the structures to a nearly uniform density.

公开(公告)号：DE112007000267T5

公开(公告)日：2009-01-22

申请号：DE112007000267

申请日：2007-01-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KNORR ANDREAS

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/065

Abstract: Vertically stacked integrated circuits and methods of fabrication thereof are disclosed. Deep vias that provide vertical electrical connection for vertically stacked integrated circuits are formed early in the manufacturing process, before integrated circuits are bonded together to form a three dimensional integrated circuit (3D-IC).