公开(公告)号：DE10248704B4

公开(公告)日：2005-02-10

申请号：DE10248704

申请日：2002-10-18

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： COSTRINI GREG ,  ECONIMIKOS LAERTIS ,  LIAN JINGVU ,  WISE MICHAEL

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/8242

Abstract: High dielectric constant (k) stacked capacitor is formed in a semiconductor memory device by forming a contact via in silicon dioxide layer covering transistor device; filling contact via with polysilicon to form polyplug in contact via; etching exposed surface of polyplug to form recess; depositing in situ a carrier layer and a first metal or metal oxide layer; and depositing high k material and to form the top electrode of stacked capacitor. Formation of high k stacked capacitor in a semiconductor memory device comprises forming a contact via in a silicon dioxide layer covering a transistor device; filling the contact via with a polysilicon to form a polyplug in the contact via; etching an exposed surface of the polyplug to form a recess; depositing in situ a carrier layer and a first metal or metal oxide layer; chemical-mechanical polishing (CMP) to leave a planarized surface with a barrier layer and metal filling the recess; depositing a second metal (112) or metal oxide layer and patterning the second metal layer to form a bottom electrode in contact with the metal within the recess; depositing a high k material and a third metal or metal oxide layer to form the top electrode of the stacked capacitor. An Independent claim is also included for a high k stacked capacitor in a semiconductor memory device comprising a silicon substrate, a polysilicon plug defining a recess, a barrier layer, metal layer deposited in situ and filing the recess, a first metal layer, a high k dielectric material, and a second metal electrode.

公开(公告)号：DE102004016963A1

公开(公告)日：2004-11-18

申请号：DE102004016963

申请日：2004-04-06

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： WISE MICHAEL ,  LIMB YOUNG ,  WONG KWONG HON ,  LIAN JENNY ,  NAGEL NICOLAS

IPC: B32B9/04 ,  B32B15/04 ,  H01L21/02 ,  H01L21/8239 ,  H01L21/8242

Abstract: Si, Al, Al plus TiN, and IrO2 are used as adhesion layers to prevent peeling of noble metal electrodes, such as Pt, from a silicon dioxide (SiO 2 ) substrate in capacitor structures of memory devices.

公开(公告)号：DE10360537A1

公开(公告)日：2004-08-05

申请号：DE10360537

申请日：2003-12-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KNORR ANDREAS ,  WISE MICHAEL

IPC: H01L21/762 ,  H01L27/108

Abstract: A method of forming deep isolation trenches in the fabrication of ICs is disclosed. The substrate is prepared with deep isolation trenches. The isolation trenches are partially filled with a first dielectric material. An etch mask layer is deposited on the substrate and used to remove excess first dielectric material on the surface of the substrate. The isolation trenches are then completely filled with a second dielectric material. Excess second dielectric material is then removed from the surface of the substrate.

公开(公告)号：DE10360537B4

公开(公告)日：2008-02-14

申请号：DE10360537

申请日：2003-12-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KNORR ANDREAS ,  WISE MICHAEL

IPC: H01L21/762 ,  H01L27/108

Abstract: A method of forming deep isolation trenches in the fabrication of ICs is disclosed. The substrate is prepared with deep isolation trenches. The isolation trenches are partially filled with a first dielectric material. An etch mask layer is deposited on the substrate and used to remove excess first dielectric material on the surface of the substrate. The isolation trenches are then completely filled with a second dielectric material. Excess second dielectric material is then removed from the surface of the substrate.

公开(公告)号：DE10248704A1

公开(公告)日：2003-05-15

申请号：DE10248704

申请日：2002-10-18

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： COSTRINI GREG ,  ECONIMIKOS LAERTIS ,  LIAN JINGVU ,  WISE MICHAEL

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/8242

Abstract: High dielectric constant (k) stacked capacitor is formed in a semiconductor memory device by forming a contact via in silicon dioxide layer covering transistor device; filling contact via with polysilicon to form polyplug in contact via; etching exposed surface of polyplug to form recess; depositing in situ a carrier layer and a first metal or metal oxide layer; and depositing high k material and to form the top electrode of stacked capacitor. Formation of high k stacked capacitor in a semiconductor memory device comprises forming a contact via in a silicon dioxide layer covering a transistor device; filling the contact via with a polysilicon to form a polyplug in the contact via; etching an exposed surface of the polyplug to form a recess; depositing in situ a carrier layer and a first metal or metal oxide layer; chemical-mechanical polishing (CMP) to leave a planarized surface with a barrier layer and metal filling the recess; depositing a second metal (112) or metal oxide layer and patterning the second metal layer to form a bottom electrode in contact with the metal within the recess; depositing a high k material and a third metal or metal oxide layer to form the top electrode of the stacked capacitor. An Independent claim is also included for a high k stacked capacitor in a semiconductor memory device comprising a silicon substrate, a polysilicon plug defining a recess, a barrier layer, metal layer deposited in situ and filing the recess, a first metal layer, a high k dielectric material, and a second metal electrode.