公开(公告)号：DE60013168D1

公开(公告)日：2004-09-23

申请号：DE60013168

申请日：2000-10-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DANIEL GABRIEL ,  WEINFURTNER OLIVER

IPC: G11C17/14 ,  G11C17/16

Abstract: A circuit for storing a bit of data is provided, where the circuit includes a first fuse having a first end and a second end and a second fuse having a third end and a fourth end. The first end of the first fuse is connected to a logic 0 input and its second end is connected to a common output. The third end of the second fuse is connected to a logic 1 input and the fourth end is connected to the common output. To store the bit of data, one of the first and second fuses is selectively blown. Hence, two fuses can be used to store a bit of information.

公开(公告)号：DE60103623D1

公开(公告)日：2004-07-08

申请号：DE60103623

申请日：2001-03-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEINFURTNER OLIVER

IPC: G11C11/4074 ,  G11C5/00

Abstract: In a flexible programmable controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a plurality of X states. A state storage device is responsive to input signals indicating a Reset state or a change in the state diagram from a current state to a next state for generating a Reset and an associated complementary Set signal or a revised plurality of X state output signals comprising a true State signal and a complementary true State signal for the next state of the plurality of X states. An output arrangement is responsive to the Reset and complementary Set signals or the true State signal and the complementary true State signal in the revised plurality of X state output signals from the state storage device for generating separate predetermined ones of M output signals associated with said Reset or next state for controlling the generator system.

公开(公告)号：DE60103622D1

公开(公告)日：2004-07-08

申请号：DE60103622

申请日：2001-03-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEINFURTNER OLIVER

IPC: G11C5/14 ,  G11C5/00

Abstract: In a controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a plurality of X states. A state storage device is responsive to input signals indicating a change in the state diagram from a current state to a next state for generating a revised plurality of X state output signals comprising a true State signal and a complementary true State signal for the next state of the plurality of X states. An output arrangement is responsive to the true State signal and the complementary true State signal in the revised plurality of X state output signals from the state storage device for generating separate predetermined ones of M output signals associated with said next state for controlling the generator system while providing substantially zero current consumption when the state diagram reaches a final state of the plurality of X states.

公开(公告)号：DE60103534D1

公开(公告)日：2004-07-01

申请号：DE60103534

申请日：2001-06-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEINFURTNER OLIVER

IPC: G05F3/24 ,  G11C5/14

Abstract: Apparatus is used to dynamically control the power output of generators of a generator system on a chip to load circuits on the chip. A power bus is directed along at least one "spine" section on the chip which may intersect with at least one "arm" section on the chip for supplying power from the generators, which are coupled to the power bus in the "spine" section thereof, to circuits on the chip. The power bus has a feedback lead from each end which is remote from the generators for providing a continuous measurement of a voltage drop occurring at each remote end. At least one detector circuit is located at a predetermined point adjacent the generators of the chip for comparing a voltage from the generators measured at the predetermined point with the concurrent voltage drop measured at an associated remote end. In response to such comparison, the at least one detector circuit generates control signals for transmission to the generators for altering a generated voltage to maintain a predetermined power level on the power bus in response to load changes caused by the circuits on the chip.

公开(公告)号：DE60101475D1

公开(公告)日：2004-01-22

申请号：DE60101475

申请日：2001-05-25

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： ELLIS WAYNE F ,  LI YUJUN ,  HSU L ,  WEINFURTNER OLIVER ,  JI L

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4078

Abstract: Improved transistor array device performance is obtained by use of bias voltage regulation which tracks with a fraction of a monitor transistor threshold voltage. The circuitry and methods are especially useful for improving the performance of transistor array devices such as DRAM and embedded DRAM. These benefits are obtained especially when at least two bias voltages normally supplied to the array are regulated by tracking with a fraction of an actual threshold voltage of at least one monitor transistor. Performance improvements include improved reliability, wider operational bias conditions, reduced power consumption and (in the case of memory cells) improved retention time.