公开(公告)号：DE60011471T2

公开(公告)日：2005-06-09

申请号：DE60011471

申请日：2000-12-13

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： HSU L ,  WEINFURTNER OLIVER ,  WORDEMAN R

IPC: H02M3/07

Abstract: A charge pump generator system and method is provided which more precisely maintains the level of an internally generated voltage supply by operating some or all of the available charge pumps depending upon the voltage level reached by the voltage supply. When the voltage supply is far from its target level, a first group and a second group of charge pumps are operated. The first group may preferably have a faster pumping rate or a greater number of charge pumps than the second group. When the voltage supply exceeds a first predetermined level, the first group of charge pumps is switched off while the second group remains on, such that the rate of charge transfer slows. The second group continues operating until a second, e.g. target, voltage level is exceeded. The slower rate of charge transfer then effective reduces overshoot, ringing and noise coupled onto the voltage supply line. Preferably, at least one charge pump operates in both standby and active modes, thereby reducing chip area.

公开(公告)号：DE60101475T2

公开(公告)日：2004-11-25

申请号：DE60101475

申请日：2001-05-25

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： ELLIS WAYNE F ,  LI YUJUN ,  HSU L ,  WEINFURTNER OLIVER ,  JI L

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4078

Abstract: Improved transistor array device performance is obtained by use of bias voltage regulation which tracks with a fraction of a monitor transistor threshold voltage. The circuitry and methods are especially useful for improving the performance of transistor array devices such as DRAM and embedded DRAM. These benefits are obtained especially when at least two bias voltages normally supplied to the array are regulated by tracking with a fraction of an actual threshold voltage of at least one monitor transistor. Performance improvements include improved reliability, wider operational bias conditions, reduced power consumption and (in the case of memory cells) improved retention time.

公开(公告)号：DE60101475D1

公开(公告)日：2004-01-22

申请号：DE60101475

申请日：2001-05-25

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： ELLIS WAYNE F ,  LI YUJUN ,  HSU L ,  WEINFURTNER OLIVER ,  JI L

IPC: G11C5/14 ,  G11C8/08 ,  G11C11/4074 ,  G11C11/4078

Abstract: Improved transistor array device performance is obtained by use of bias voltage regulation which tracks with a fraction of a monitor transistor threshold voltage. The circuitry and methods are especially useful for improving the performance of transistor array devices such as DRAM and embedded DRAM. These benefits are obtained especially when at least two bias voltages normally supplied to the array are regulated by tracking with a fraction of an actual threshold voltage of at least one monitor transistor. Performance improvements include improved reliability, wider operational bias conditions, reduced power consumption and (in the case of memory cells) improved retention time.

公开(公告)号：DE69817114T2

公开(公告)日：2004-06-09

申请号：DE69817114

申请日：1998-08-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEINFURTNER OLIVER

IPC: G11C11/407 ,  G05F1/46 ,  G05F1/56 ,  H01L21/822 ,  H01L27/04

Abstract: A method for reducing the current consumption of a reference voltage circuit while a synchronous DRAM is in standby power-down mode is provided. The reference voltage is stored on a capacitor within the DRAM circuit. The reference voltage circuit is selectively disconnected from, and reconnected to the Vref-node at predetermined time intervals during a power down mode, in order to ensure leakage compensation. When the power down mode exceeds a predetermined time, the reference voltage circuit is disabled to further reduce the current consumption.

公开(公告)号：DE69809013T2

公开(公告)日：2003-06-18

申请号：DE69809013

申请日：1998-07-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEINFURTNER OLIVER

IPC: G05F1/56 ,  G05F1/46 ,  G11C5/14 ,  H03K17/06

Abstract: A voltage converter circuit for an electronic device includes a transistor switch (140) for providing current pulses to a current input node. The transistor switch has a gate (128) and a turn-on threshold voltage. An adjustment circuit (114) provides a controlled voltage to the gate for turning on the transistor switch and the adjustment circuit includes a subcircuit for compensating for variations in the turn-on threshold voltage of the transistor switch. A timer (16) for enables the adjustment circuit for a preset period of time.

公开(公告)号：DE60103622T2

公开(公告)日：2005-08-25

申请号：DE60103622

申请日：2001-03-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEINFURTNER OLIVER

IPC: G11C5/14 ,  G11C5/00

Abstract: In a controller for controlling a generator system on a memory chip, the controller operates as a state machine in accordance with a state diagram including a plurality of X states. A state storage device is responsive to input signals indicating a change in the state diagram from a current state to a next state for generating a revised plurality of X state output signals comprising a true State signal and a complementary true State signal for the next state of the plurality of X states. An output arrangement is responsive to the true State signal and the complementary true State signal in the revised plurality of X state output signals from the state storage device for generating separate predetermined ones of M output signals associated with said next state for controlling the generator system while providing substantially zero current consumption when the state diagram reaches a final state of the plurality of X states.

公开(公告)号：DE60103534T2

公开(公告)日：2005-06-30

申请号：DE60103534

申请日：2001-06-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEINFURTNER OLIVER

IPC: G05F3/24 ,  G11C5/14

Abstract: Apparatus is used to dynamically control the power output of generators of a generator system on a chip to load circuits on the chip. A power bus is directed along at least one "spine" section on the chip which may intersect with at least one "arm" section on the chip for supplying power from the generators, which are coupled to the power bus in the "spine" section thereof, to circuits on the chip. The power bus has a feedback lead from each end which is remote from the generators for providing a continuous measurement of a voltage drop occurring at each remote end. At least one detector circuit is located at a predetermined point adjacent the generators of the chip for comparing a voltage from the generators measured at the predetermined point with the concurrent voltage drop measured at an associated remote end. In response to such comparison, the at least one detector circuit generates control signals for transmission to the generators for altering a generated voltage to maintain a predetermined power level on the power bus in response to load changes caused by the circuits on the chip.

公开(公告)号：DE69817114D1

公开(公告)日：2003-09-18

申请号：DE69817114

申请日：1998-08-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WEINFURTNER OLIVER

IPC: G11C11/407 ,  G05F1/46 ,  G05F1/56 ,  H01L21/822 ,  H01L27/04

Abstract: A method for reducing the current consumption of a reference voltage circuit while a synchronous DRAM is in standby power-down mode is provided. The reference voltage is stored on a capacitor within the DRAM circuit. The reference voltage circuit is selectively disconnected from, and reconnected to the Vref-node at predetermined time intervals during a power down mode, in order to ensure leakage compensation. When the power down mode exceeds a predetermined time, the reference voltage circuit is disabled to further reduce the current consumption.

公开(公告)号：DE10258780A1

公开(公告)日：2003-07-10

申请号：DE10258780

申请日：2002-12-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREY ULRICH ,  LEHMANN GUNTHER ,  WEINFURTNER OLIVER

IPC: G11C17/18 ,  H03K17/00

Abstract: An anti-fuse system composed of a multiplicity of anti-fuse circuits (24, 26, 28, N) connected across a voltage source (10) by a pair of conductors (16, 18). Each anti-fuse circuit comprising an anti-fuse (30) connected in a series with a blow or control transistor (36) and a control circuit (44) for monitoring the status of the anti-fuse (30), Control circuit (44) provides an "on" signal to the gate (38) of control transistor (36) only when a_"select_" signal is received at an input (46) of control circuit (44) and if anti-fuse (30) has not been blown. After the anti-fuse (30) is blown, control circuit (44) turns off the control transistor (36) thereby providing a constant power source voltage across each anti-fuse circuit (24, 26, 28, N) regardless of the number of parallel anti-fuses which have been blown.

公开(公告)号：DE60013168T2

公开(公告)日：2005-08-11

申请号：DE60013168

申请日：2000-10-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DANIEL GABRIEL ,  WEINFURTNER OLIVER

IPC: G11C17/14 ,  G11C17/16

Abstract: A circuit for storing a bit of data is provided, where the circuit includes a first fuse having a first end and a second end and a second fuse having a third end and a fourth end. The first end of the first fuse is connected to a logic 0 input and its second end is connected to a common output. The third end of the second fuse is connected to a logic 1 input and the fourth end is connected to the common output. To store the bit of data, one of the first and second fuses is selectively blown. Hence, two fuses can be used to store a bit of information.