公开(公告)号：AU2003293828A8

公开(公告)日：2004-07-09

申请号：AU2003293828

申请日：2003-12-10

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GOGL DIETMAR ,  SCHEUERLEIN ROY EDWIN ,  REOHR WILLIAM ROBERT

IPC: G11C11/16

Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.

公开(公告)号：DE60304209T2

公开(公告)日：2006-12-14

申请号：DE60304209

申请日：2003-10-28

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  HOENIGSCHMID HEINZ

IPC: G11C11/16 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/22

Abstract: A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure. In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch is connected to the conductor associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.

公开(公告)号：DE60304209D1

公开(公告)日：2006-05-11

申请号：DE60304209

申请日：2003-10-28

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  HOENIGSCHMID HEINZ

IPC: G11C11/16 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/22

Abstract: A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure. In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch is connected to the conductor associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.

公开(公告)号：DE60320301D1

公开(公告)日：2008-05-21

申请号：DE60320301

申请日：2003-12-10

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  SCHEUERLEIN ROY EDWIN ,  REOHR WILLIAM ROBERT

IPC: G11C11/16

Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.

公开(公告)号：DE60305208T2

公开(公告)日：2006-12-14

申请号：DE60305208

申请日：2003-12-17

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  REOHR ROBERT

IPC: G11C7/06 ,  G11C7/18

Abstract: A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors. Alternatively, the load device may be a hard-wired current mirror, and a multiplexer may be used to select whether the first input signal or the second input signal is connected to a first or second side of the current mirror. Configurable dummy loads may be added at appropriate nodes to optimize the capacitive load and increase the speed of the amplifier. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal and the second input signal.

公开(公告)号：DE102006001117A1

公开(公告)日：2006-08-17

申请号：DE102006001117

申请日：2006-01-09

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  LAMMERS STEFAN ,  VIEHMANN HANS-HEINRICH

IPC: G11C11/15 ,  G11C7/12

Abstract: A calibrated magnetic random access memory (MRAM) current sense amplifier includes a first plurality of trim transistors selectively configured in parallel with a first load device, the first load device associated with a data side of the sense amplifier. A second plurality of trim transistors is selectively configured in parallel with a second load device, the second load device associated with a reference side of the sense amplifier. The first and said second plurality of trim transistors are individually activated so as to compensate for device mismatch with respect to the data and reference sides of the sense amplifier.

公开(公告)号：WO0239454A3

公开(公告)日：2002-12-19

申请号：PCT/EP0112622

申请日：2001-10-31

Applicant: INFINEON TECHNOLOGIES AG ,  FREITAG MARTIN ,  HOENIGSCHMID HEINZ ,  GOGL DIETMAR ,  LAMMERS STEFAN

Inventor： FREITAG MARTIN ,  HOENIGSCHMID HEINZ ,  GOGL DIETMAR ,  LAMMERS STEFAN

IPC: H01L27/105 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/22 ,  H01L43/08 ,  G11C11/15

CPC classification number: H01L27/222 ,  B82Y10/00 ,  G11C11/16

Abstract: The form of the supply lines in a cell field made from a matrix of columned and lined supply lines of a plurality of magnetic memory cells is optimised by diverging from a quadratic cross-section of the supply lines so that the magnetic field component Bx of the writing currents arranged on the plane of the cell field is rapidly reduced at an increasing distance from the increasing point of intersection.

Abstract translation: 从列和行的矩阵一个建成的引线的形状导致的多个磁存储单元的单元阵列被偏离引线的方形横截面的优化，使得磁场分量从交叉点Bx的随着距离的增加躺在单元阵列平面中的写电流的足够快地 降低。

公开(公告)号：WO02073618A3

公开(公告)日：2003-05-01

申请号：PCT/DE0200897

申请日：2002-03-13

Applicant: INFINEON TECHNOLOGIES AG ,  GOGL DIETMAR ,  VIEHMANN HANS-HEINRICH

Inventor： GOGL DIETMAR ,  VIEHMANN HANS-HEINRICH

IPC: G11C11/15 ,  G11C7/06 ,  G11C11/16

CPC classification number: G11C7/067 ,  G11C7/062 ,  G11C2207/063

Abstract: A memory sense amplifier (10) for a semiconductor memory device (1) is provided with a compensation current source device (30) which generates a compensation current (Icomp) and feeds it to an interconnected bit line (4). Said compensation current (Icomp) is selected in such a manner that during readout a potential gradient can be generated and/or maintained in cooperation with a compensation voltage source device (20) on the selected and interlinked bit line device (4) that is substantially constant over time.

Abstract translation: 在读出放大器装置（10），用于半导体存储器设备（1）是一个补偿电流源装置（30）设置，通过它可产生一个补偿电流（ICOMP），并且可以提供相关联的位线（4），所述补偿电流（ICOMP）被选择，使得当 是（4）具有可以产生预期的补偿电压源装置（20）到所选择的和连接的位线大致时间上恒定的电势差和/或维持耐久性合作公吨读取操作。

公开(公告)号：WO02084705A3

公开(公告)日：2003-05-01

申请号：PCT/DE0201255

申请日：2002-04-05

Applicant: INFINEON TECHNOLOGIES AG ,  GOGL DIETMAR ,  SCHLOESSER TILL

Inventor： GOGL DIETMAR ,  SCHLOESSER TILL

IPC: G11C11/15 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

CPC classification number: G11C11/15

Abstract: The invention relates to a method for operating an MRAM semiconductor memory arrangement, whereby, in order to read stored information, reversible magnetic changes are carried out on the TMR cells (TMR1, TMR2, ...) and a corresponding transient changed current compared with the original read signal. The TMR memory cell itself can thus serve as reference, although the information in the TMR memory cell is not destroyed, in other words the same must not be back-written. The invention is used to advantage in an MRAM memory arrangement, in which several TMR cells (TMR1, ..., TMR4) are connected in parallel to a selection transistor (TR1) and in which a write line (WL1, WL2), not electrically connected to the memory cell, is provided.

Abstract translation: 在用于读取到TMR细胞（TMR1，TMR2，...）存储的信息可逆磁变化操作MRAM半导体存储器件本发明的方法被执行，并且其结果是简要地改变流与原始读信号相比较。 其特征在于所述TMR存储单元本身可以作为参考，虽然信息是在TMR存储单元不被破坏，即 它不能被恢复。 本发明优选适用于MRAM存储器布置，其中多个TMR单元（TMR1，...，TMR4）平行于选择晶体管（TR1）被连接，并且在其中写入线没有电连接到存储单元（WL1，WL2 ）是否存在。

公开(公告)号：DE102006006792B3

公开(公告)日：2007-05-16

申请号：DE102006006792

申请日：2006-02-14

Applicant: INFINEON TECHNOLOGIES AG ,  ALTIS SEMICONDUCTOR SNC

Inventor： GOGL DIETMAR

IPC: G11C16/02

Abstract: The memory has memory cells that are connected with plate lines and with two bit lines (14, 15). A switch (20) has control inputs that are connected with word lines (16, 17). The bit lines are connected with another switch (21), which connects the bit lines with two voltage levels. The bit lines are connected with a read amplifier (7) that amplifies the voltage drop between the bit lines. A resistance unit (18) changes the resistance based on an electrical voltage, where one of the voltage levels lies between the plate voltage level of the plate lines and another voltage level. An independent claim is also included for a method for reading-out data from a memory cell of a memory.