公开(公告)号：WO2004055821A3

公开(公告)日：2004-11-04

申请号：PCT/EP0314011

申请日：2003-12-10

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： GOGL DIETMAR ,  SCHEUERLEIN ROY EDWIN ,  REOHR WILLIAM ROBERT

IPC: G11C11/16

CPC classification number: G11C11/1693 ,  G11C11/1673 ,  G11C11/1675

Abstract: A magnetic memory circuit comprises a plurality of memory cells and a plurality of bit lines coupled to the memory cells for selectively accessing one or more of the memory cells. The memory circuit comprises at least one bit line programming circuit, configurable as a current source for generating a programming current for writing a logical state of at least one memory cell and/or a current sink for returning the programming current, and a first set of switches. The first set of switches are disabled at least during a read operation of the memory cells and at least a portion of the first set of switches are selectively enabled during a write operation of the memory cells. Each switch in the first set of switches is configured to selectively couple the at least one bit line programming circuit to a corresponding one of the bit lines in response to a first control signal. The memory circuit further comprises at least one sense amplifier and a second set of switches. The second set of switches are disabled at least during a write operation of the memory cells and at least a portion of the second set of switches are selectively enabled during a read operation of the memory cells. Each switch in the second set of switches is configured to selectively couple the at least one sense amplifier to a corresponding one of the bit lines in response to a second control signal.

Abstract translation: 磁存储器电路包括多个存储器单元和耦合到存储器单元的多个位线，用于选择性地访问一个或多个存储器单元。 存储器电路包括至少一个位线编程电路，可配置为用于产生用于写入至少一个存储器单元的逻辑状态的编程电流的电流源和/或用于返回编程电流的电流吸收器，以及第一组 开关。 至少在存储器单元的读取操作期间禁用第一组开关，并且在存储器单元的写入操作期间选择性地使能第一组开关的至少一部分。 第一组开关中的每个开关被配置为响应于第一控制信号选择性地将至少一个位线编程电路耦合到对应的位线。 存储器电路还包括至少一个读出放大器和第二组开关。 至少在存储器单元的写入操作期间禁用第二组开关，并且在存储器单元的读取操作期间，第二组开关的至少一部分被选择性地使能。 第二组开关中的每个开关被配置为响应于第二控制信号选择性地将至少一个读出放大器耦合到对应的一个位线。

公开(公告)号：JP2002124080A

公开(公告)日：2002-04-26

申请号：JP2001235533

申请日：2001-08-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C5/06 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide a device performing write-in in which loss of MRAM is less and in which memory cells having large resistance, short word lines and/or bit lines are not utilized. SOLUTION: This device has many memory cells (Z0, Z1, etc.), and these memory cells are provided respectively in a memory cell field between a word line(WL) and bit lines (BL, BL0, BL1, etc.). At the time of write-in process for the prescribed memory cell, voltage drop (V1-V2) is caused in the selected word line(WL) connected to this memory cell. When voltage V1 or voltage V2

公开(公告)号：JP2002134708A

公开(公告)日：2002-05-10

申请号：JP2001211245

申请日：2001-07-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  ROEHR THOMAS ,  HOENIGSCHMID HEINZ

IPC: G11C11/14 ,  G11C7/18 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To reduce nonconforming action caused by overcoupling among the adjacent lines in a memory matrix, comprising a cell field composed of row lines and column lines in which the memory elements are situated at each point, where the row lines and column lines intersect one another, and the column line and/or row lines of the cell field are placed adjacent to each other. SOLUTION: This memory matrix is constituted, such that the order of row lines or column lines are equal in the edges of the memory matrix counterposed to each other regarding changes in the configurational constitution of the lines. As a result of this, additional circuit cost for executing address decoding, namely an additional circuit cost generated when an address line is not assigned correspondingly or it has a different order from the original order is avoided. For the case of MRAM, the connection constitution of the row lines and column lines in both edges of a cell field becomes advantageous. Furthermore, the cell field or its row lines and/or column line is made symmetrical by a mirror image, regarding changes in their arrangement constitution.

公开(公告)号：JP2002093144A

公开(公告)日：2002-03-29

申请号：JP2001197558

申请日：2001-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  GOGL DIETMAR ,  MUELLER GERHARD ,  LOEER THOMAS

IPC: G11C11/14 ,  G11C7/12 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide a current driver arrangement capable of supplying a large current at a low voltage when the area needs to be small. SOLUTION: In a current driver arrangement described in the above, this problem can be solved by configuring a driver of an n-type field effect transistor and a current source connected in series therewith. Concretely, a current driver arrangement for an MRAM is provided comprising a memory cell field having a plurality of memory cells (Z) at the crossing position of a word line (WL) and a bit line (BL), and drivers (T1, T2) supplied to each end of the above word line (WL) and the above bit line (BL), and allocated to the above word line (WL) and the above bit line (BL).

公开(公告)号：JP2002203388A

公开(公告)日：2002-07-19

申请号：JP2001331484

申请日：2001-10-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FREITAG MARTIN ,  LAMMERS STEFAN ,  GOGL DIETMAR ,  ROEHR THOMAS

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide a method for obstructing undesirable programming in a MRAM device so that disablement of programming owing to scattered magnetic field of a memory cell being adjacent to a selection memory cell can be surely and simply obstructed. SOLUTION: A current IBL2 flowing in a bit line BL2 generates a scattered magnetic field in a MTJ memory cell I3 in an intersection part of a bit line BL3 and a word line WL1. Then an adequate compensation current IBL3 is made to flow in the bit line BL3 to suppress influence of this scattered magnetic field, scattered magnetic field in the MTJ memory cell I3 can be canceled by compensation magnetic field generated by this compensation current IBL3.

公开(公告)号：JP2002164515A

公开(公告)日：2002-06-07

申请号：JP2001275812

申请日：2001-09-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  GOGL DIETMAR ,  FREITAG MARTIN ,  LAMMERS STEFAN

IPC: G11C11/14 ,  G11C5/02 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/22 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide an MRAM module structure wherein high packing density of memory cell sections is achieved. SOLUTION: This MRAM module structure is constituted of a plurality of memory cell sections (A, P). The respective memory cell sections (A, P) are constituted of memory arrays (A) having a plurality of memory cells (WML, TL, HML) and peripheral circuits (P) surrounding edges of the memory arrays (A). The peripheral circuits (P) surround the memory arrays (A) in such a manner that the respective memory cell sections (A, P) have a cross structure in a plane, essentially. The memory cell sections (A, P) are so nested in each other that the memory cell sections (A, P) are offset mutually on individual rows (1, 2, 3).

公开(公告)号：JP2002157874A

公开(公告)日：2002-05-31

申请号：JP2001253609

申请日：2001-08-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOGL DIETMAR ,  SCHLOSSER TILL

IPC: G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To provide an MRAM arrangement in which a cross point structure having advantages of a transistor memory cell is present in common in all possible large areas. SOLUTION: TMR-memory cells 1 to 4 and 5 to 8 are interposed between a bit line BL and word lines WL1 and WL2, respectively. Memory cells 1 to 8 include an soft magnetic layer, a tunnel resistive layer, and a hard magnetic layer. The ends of the TMR-memory cells 1 to 4 and 5 to 8 are connected to the drains or the source of switching transistors Tr1 and Tr2, respectively. The gates of the switching transistors Tr1 and Tr2 are connected to the word lines WL1 and WL2, respectively. Four TMR-memory cells 1 to 4 or 5 to 8 are connected to one switching transistor Tr1 or Tr2, respectively.

公开(公告)号：JP2002133855A

公开(公告)日：2002-05-10

申请号：JP2001241347

申请日：2001-08-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BOEHM THOMAS ,  ROEHR THOMAS ,  GOGL DIETMAR

IPC: G11C11/14 ,  G11C8/08 ,  G11C8/10 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L43/08

Abstract: PROBLEM TO BE SOLVED: To reduce the complexity and occupancy area of wirings in a driver circuit for word lines of a memory matrix. SOLUTION: In the electronic driver circuit for the word lines WL in the memory matrix 3, a driver source 2, for example, coded output sides IV0-IV3 of a current/voltage source are connected to selected word lines WLi-2-WLi+1. In this case, the word lines WL are selected for every block by control signals SLNP, SLN1, SLN2, and the outputs of the driver source 2 are applied to them. In that case, each activated word line WLi is selected by the coding of the driver source 2.

公开(公告)号：DE60305208D1

公开(公告)日：2006-06-14

申请号：DE60305208

申请日：2003-12-17

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  REOHR ROBERT

IPC: G11C7/06 ,  G11C7/18

Abstract: A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors. Alternatively, the load device may be a hard-wired current mirror, and a multiplexer may be used to select whether the first input signal or the second input signal is connected to a first or second side of the current mirror. Configurable dummy loads may be added at appropriate nodes to optimize the capacitive load and increase the speed of the amplifier. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal and the second input signal.

公开(公告)号：AU2003294886A8

公开(公告)日：2004-07-14

申请号：AU2003294886

申请日：2003-12-17

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  REOHR WILLIAM ROBERT

IPC: G11C7/06 ,  G11C7/18

Abstract: A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors. Alternatively, the load device may be a hard-wired current mirror, and a multiplexer may be used to select whether the first input signal or the second input signal is connected to a first or second side of the current mirror. Configurable dummy loads may be added at appropriate nodes to optimize the capacitive load and increase the speed of the amplifier. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal and the second input signal.