公开(公告)号：WO2004112048A3

公开(公告)日：2005-04-07

申请号：PCT/EP2004006019

申请日：2004-06-03

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  DEBROSSE JOHN ,  HOENIGSCHMID HEINZ ,  LEUSCHNER RAINER ,  MUELLER GERHARD

Inventor： DEBROSSE JOHN ,  HOENIGSCHMID HEINZ ,  LEUSCHNER RAINER ,  MUELLER GERHARD

IPC: G06F11/10 ,  G11C7/24 ,  G11C11/406 ,  G11C29/00 ,  G11C11/15

CPC classification number: G11C7/24 ,  G06F11/106 ,  G11C11/406

Abstract: The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.

Abstract translation: 本发明涉及一种用于减少磁阻随机存取存储器（MRAM）中的数据错误的方法和装置。 根据所公开的方法，将数据位和相关联的纠错码（ECC）校验位存储到存储区域中。 此后，读出数据位和ECC校验位，并检测和校正任何错误。 然后基于计数开始数据刷新，然后通过访问存储的数据位和相关联的ECC校验位来刷新存储在存储区域中的相关ECC校验位，并且最终通过检查，校正和恢复数据位 并将ECC校验位存储到存储区域。

公开(公告)号：WO2005004162A3

公开(公告)日：2005-03-31

申请号：PCT/EP2004006190

申请日：2004-06-08

Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  DEBROSSE JOHN ,  LAMMERS STEFAN ,  VIEHMANN HANS-HEINRICH

Inventor： DEBROSSE JOHN ,  LAMMERS STEFAN ,  VIEHMANN HANS-HEINRICH

IPC: G11C11/15 ,  G11C11/16

CPC classification number: G11C11/15

Abstract: A method of storing information in a cross-point magnetic memory array and a cross-point magnetic memory device structure. The voltage drop across magnetic tunnel junctions (MTJ's) during a write operation is minimized to prevent damage to the MTJ's of the array. The voltage drop across the selected MTJ's, the unselected MTJ's, or both, is minimized during a write operation, reducing stress across the MTJ's, decreasing leakage currents, decreasing power consumption and increasing the write margin.

Abstract translation: 一种将信息存储在交叉点磁存储器阵列和交叉点磁存储器装置结构中的方法。 在写入操作期间磁隧道结（MTJ）上的电压降被最小化以防止损坏阵列的MTJ。 在写入操作期间，选定的MTJ，未选定的MTJ或两者上的电压降最小化，减小MTJ上的应力，降低泄漏电流，降低功耗并增加写入裕度。

公开(公告)号：DE60304209T2

公开(公告)日：2006-12-14

申请号：DE60304209

申请日：2003-10-28

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  HOENIGSCHMID HEINZ

IPC: G11C11/16 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/22

Abstract: A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure. In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch is connected to the conductor associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.

公开(公告)号：DE60304209D1

公开(公告)日：2006-05-11

申请号：DE60304209

申请日：2003-10-28

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  HOENIGSCHMID HEINZ

IPC: G11C11/16 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/22

Abstract: A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure. In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch is connected to the conductor associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.

公开(公告)号：DE602004021187D1

公开(公告)日：2009-07-02

申请号：DE602004021187

申请日：2004-06-03

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DEBROSSE JOHN ,  HOENIGSCHMID HEINZ ,  LEUSCHNER RAINER ,  MUELLER GERHARD

IPC: G11C29/00 ,  G06F11/10 ,  G11C7/24 ,  G11C11/15 ,  G11C11/406

Abstract: The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.

公开(公告)号：DE102004014244A1

公开(公告)日：2004-11-25

申请号：DE102004014244

申请日：2004-03-24

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： BUKOFSKY SCOTT ,  DEBROSSE JOHN ,  HUG MARCO ,  LIEBMANN LARS W ,  NICKEL DANIEL JOHN ,  PREUNINGER JUERGEN

IPC: G03F1/30 ,  G03F7/20 ,  G03F9/00 ,  G03F1/00

Abstract: A phase shift mask shape that reduces line-end shortening at the critical feature without changing layout size increases required of requisite phase shift rules. The phase feature is given an angled extension, which includes the lithographic shortening value. This allows the critical shape to be designed much closer to the reference layer then it could without the angled extension feature. Phase mask extension features beyond a given device segment are significantly reduced by lengthening the feature along an uncritical portion; moving the feature reference point to the device layer; and flattening the phase extension feature into an L-shape or T-shape along the uncritical parts of a device segment. Applying these design rules allows a draw of the gate conductor under current conditions and puts phase shapes inside without extending the gate conductor dimensions to the next feature.

公开(公告)号：DE69841838D1

公开(公告)日：2010-09-30

申请号：DE69841838

申请日：1998-06-29

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： HOENIGSCHMID HEINZ ,  DEBROSSE JOHN

IPC: H01L21/8242 ,  H01L27/108 ,  G11C11/4097

公开(公告)号：DE60305208D1

公开(公告)日：2006-06-14

申请号：DE60305208

申请日：2003-12-17

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  REOHR ROBERT

IPC: G11C7/06 ,  G11C7/18

Abstract: A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors. Alternatively, the load device may be a hard-wired current mirror, and a multiplexer may be used to select whether the first input signal or the second input signal is connected to a first or second side of the current mirror. Configurable dummy loads may be added at appropriate nodes to optimize the capacitive load and increase the speed of the amplifier. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal and the second input signal.

公开(公告)号：AU2003294886A8

公开(公告)日：2004-07-14

申请号：AU2003294886

申请日：2003-12-17

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  REOHR WILLIAM ROBERT

IPC: G11C7/06 ,  G11C7/18

Abstract: A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors. Alternatively, the load device may be a hard-wired current mirror, and a multiplexer may be used to select whether the first input signal or the second input signal is connected to a first or second side of the current mirror. Configurable dummy loads may be added at appropriate nodes to optimize the capacitive load and increase the speed of the amplifier. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal and the second input signal.

公开(公告)号：DE60305208T2

公开(公告)日：2006-12-14

申请号：DE60305208

申请日：2003-12-17

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  REOHR ROBERT

IPC: G11C7/06 ,  G11C7/18

Abstract: A symmetrical high-speed current sense amplifier having complementary reference cells and configurable load devices that eliminates architecture-related capacitive mismatch contributions. The current sense amplifier is adapted for use in a symmetric sensing architecture and includes a configurable load device. The current sense amplifier includes a voltage comparator, a first clamping device coupled between a first input of the voltage comparator and a first input signal, the first clamping device being coupled to a reference voltage. A second clamping device is coupled between the second input of the voltage comparator and a second input signal, the second clamping device being coupled to the reference voltage. The load device may comprise a current mirror that is coupled between the first and second input of the voltage comparator. The current mirror may be configurable by select transistors. Alternatively, the load device may be a hard-wired current mirror, and a multiplexer may be used to select whether the first input signal or the second input signal is connected to a first or second side of the current mirror. Configurable dummy loads may be added at appropriate nodes to optimize the capacitive load and increase the speed of the amplifier. Equalization devices may be coupled between the first and second inputs of the voltage comparator, and between the first input signal and the second input signal.