公开(公告)号：JP2004006772A

公开(公告)日：2004-01-08

申请号：JP2003093635

申请日：2003-03-31

Applicant: IBM ,  SIEMENS AG

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  KIEWRA EDWARD ,  RADENS CARL

IPC: B23K26/00 ,  B23K26/38 ,  B23K101/38 ,  H01H69/02 ,  H01H85/00 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/525 ,  H01L27/04 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit having an improved fuse structure part and laser fuse links. SOLUTION: The fuse structure part in an integrated circuit chip comprises an insulated semiconductor substrate, a fuse bank 410 which is constituted of a plurality of the parallel fuse links 402, 404 and 404 on the same plane and which are integrated with the insulated semiconductor substrate and voids 410 and 412 which scatter between pairs of fuse links and which extend across the plane delimited by the fuse links on the same plane. The voids 410 and 412 surrounding a spot 420 to be hit by a laser beam during a fusing operation function as crack stops for preventing damage against an adjacent circuit element or the other existing fuse link. Thus, a denser pitch between fuses can be obtained by suitably forming and positioning the voids. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2000323578A

公开(公告)日：2000-11-24

申请号：JP37247499

申请日：1999-12-28

Applicant: IBM ,  SIEMENS AG

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  KIEWRA EDWARD ,  RADENS CARL

IPC: B23K26/00 ,  B23K26/38 ,  B23K101/38 ,  H01H69/02 ,  H01H85/00 ,  H01L21/3205 ,  H01L21/82 ,  H01L21/8242 ,  H01L23/52 ,  H01L23/525 ,  H01L27/04 ,  H01L27/108 ,  H01H85/046

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an integrated circuit which has a improved fuse structure and a laser fuse link. SOLUTION: A fuse structure within an integrated circuit chi is described which includes an insulated semiconductor substrate, a fuse band 4 consisting of a plurality of parallel fuse links 402, 404, and 406 on the same plane and united with the insulated semiconductor substrate, and voids 410 and 412 scattered among fuse links each in a pair and extending beyond the plane demarcated by the fuse links on the same plane. The voids 410 and 412, surrounding the spot 420 which should be hit with a laser beam during the operation of fuse fusion function as crack stopper for preventing damages to the adjacent circuit element or other existing fuse link. Closer pitch between fuses can be obtained by forming and positioning the voids properly.

公开(公告)号：JP2000252364A

公开(公告)日：2000-09-14

申请号：JP2000047093

申请日：2000-02-24

Applicant: IBM ,  SIEMENS AG

Inventor： BRINTZINGER AXEL ,  KIEWRA EDWARD W ,  NARAYAN CHANDRASEKHAR ,  KAARU JIEI RADENSU

IPC: H01L21/82 ,  G11C29/04 ,  H01H85/00 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/02 ,  H01L27/108 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a fuse link structure which reduces the magnitude of damage which is caused when a fuse element is blown and to provide its method. SOLUTION: This integrated circuit is provided with a main element 102. The integrated circuit is provided with a redundant element 104 which is replaced selectively with the main element 102 by at lease one fuse. The fuse contains a first layer 401 which comprises at least one fuse link region 402, contains a second layer 401 on the first layer, a gap 410 inside the second layer on the fuse link region 402, and contains a fuse window 408 in a dielectric layer 407. Since the gap 410 guides energy and a fuse material to the fuse window 408 from the fuse link region 402, it is possible to reduce damage to a circumferential structure.

公开(公告)号：JP2000091438A

公开(公告)日：2000-03-31

申请号：JP23860699

申请日：1999-08-25

Applicant: SIEMENS AG ,  IBM

Inventor： NARAYAN CHANDRASEKHAR ,  BRINTZINGER AXEL ,  DANIEL GABRIEL ,  EINSPRUCH FRED

IPC: H01L21/82 ,  G11C29/04 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/00 ,  H01L27/108 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To enable electrical fusion at the voltage of a specific value by connecting a fuse link at its one end with an individual connector terminal having a sectional region larger than its sectional region, and by connecting the fuse link at its other end with a common connector terminal having a sectional region which is larger than that of the sectional region of the individual connector terminal. SOLUTION: A semiconductor device 40 includes a board 41, on whose surface there is provided a redundant operating wiring, including many fuse-links 44 or a fuse bank used as a severe pitch array 42 for custom wirings. The fuse link 44 is connected at its one end with an individual connector terminal 43, having a sectional region about twice as large as its sectional region to be connected at its other end, with a common connector terminal 45 having a sectional region about twice as large as that of the individual connector terminal 43. As a result, heating caused by the maximized resistance difference between the fuse link 44 and the common connector terminal 45 is promoted to make possible electrical fusion at a voltage of about 10 V.

公开(公告)号：DE60011190D1

公开(公告)日：2004-07-08

申请号：DE60011190

申请日：2000-07-25

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： NARAYAN CHANDRASEKHAR ,  ARNDT KENNETH ,  KIRIHATA TOSHIAKI ,  DANIEL GABRIEL ,  LACHTRUPP DAVID ,  BRINTZINGER AXEL

IPC: H01L21/82 ,  H01H85/00 ,  H01H85/02 ,  H01H85/044 ,  H01H85/046 ,  H01L21/66 ,  H01L23/525 ,  H01L27/02

Abstract: A plurality of fuses of different types, each type of fuse serving a specific purpose are positioned on a semiconductor integrated circuit wafer, wherein activating one type of fuse does not incapacitate fuses of a different type. Fuses of the first type, e.g., laser activated fuses, are primarily used for repairing defects at the wafer level, whereas fuses of the second type, e.g., electrically activated fuses, are used for repairing defects found after mounting the IC chips on a module and stressing the module at burn-in test. Defects at the module level typically are single cell failures which are cured by the electrically programmed fuses to activate module level redundancies.

公开(公告)号：DE102004025108B4

公开(公告)日：2019-11-28

申请号：DE102004025108

申请日：2004-05-21

Applicant: IBM ,  SAMSUNG ELECTRONICS CO LTD

Inventor： BRINTZINGER AXEL ,  TONTI WILLIAM ,  RADENS CARL J

IPC: H01L23/525 ,  H01L21/60 ,  H01L21/762

Abstract: Antifuse, die folgendes umfasst:ein Halbleitersubstrat mit einem aktiven Bereich (152; 202; 302), der von einer Grenze (154; 204; 304) einer Flachgrabenisolation umgeben ist;einen über dem Halbleitersubstrat angeordneten und über zumindest einem Teil der Grenze der Flachgrabenisolation liegenden Gateleiter (156; 206; 306);ein zwischen dem Halbleitersubstrat und dem Gateleiter angeordnetes Dielektrikum (157);einen ersten an den Gateleiter gekoppelten Anschluss (158); undeinen zweiten an das Halbleitersubstrat gekoppelten Anschluss (160),wobei der von der Grenze der Flachgrabenisolation umgebene aktive Bereich des Halbleitersubstrates ein längliches Glied (152A; 302A) und mehrere Fingerteile (152B; 302B) enthält, die sich von dem länglichen Glied des aktiven Bereichs erstrecken und quer zu dem länglichen Glied des aktiven Bereichs derart verlaufen, daß der Gateleiter zumindest über einem Teil von zumindest einigen der Fingerteile (152B; 302B) des aktiven Bereichs liegt, undwobei der Gateleiter (156; 206; 306) ein längliches Glied (306A) und mehrere Fingerteile (306B) enthält, die sich von dem länglichen Glied des Gateleiters erstrecken und quer zu dem länglichen Glied des Gateleiters verlaufen.

公开(公告)号：DE60011190T2

公开(公告)日：2005-06-30

申请号：DE60011190

申请日：2000-07-25

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： NARAYAN CHANDRASEKHAR ,  ARNDT KENNETH ,  KIRIHATA TOSHIAKI ,  DANIEL GABRIEL ,  LACHTRUPP DAVID ,  BRINTZINGER AXEL

IPC: H01L21/82 ,  H01H85/00 ,  H01H85/02 ,  H01H85/044 ,  H01H85/046 ,  H01L21/66 ,  H01L23/525 ,  H01L27/02

Abstract: A plurality of fuses of different types, each type of fuse serving a specific purpose are positioned on a semiconductor integrated circuit wafer, wherein activating one type of fuse does not incapacitate fuses of a different type. Fuses of the first type, e.g., laser activated fuses, are primarily used for repairing defects at the wafer level, whereas fuses of the second type, e.g., electrically activated fuses, are used for repairing defects found after mounting the IC chips on a module and stressing the module at burn-in test. Defects at the module level typically are single cell failures which are cured by the electrically programmed fuses to activate module level redundancies.

公开(公告)号：DE102004025108A1

公开(公告)日：2005-03-10

申请号：DE102004025108

申请日：2004-05-21

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL ,  TONTI WILLIAM ,  RADENS CARL J

IPC: H01L23/525 ,  H01L21/60 ,  H01L21/762

Abstract: Methods and apparatus for providing an antifuse are disclosed, where the antifuse includes a semiconductor substrate having an active area circumscribed by a shallow trench isolation (STI) boundary; a gate conductor disposed above the semiconductor substrate and overlying at least a portion of the STI boundary; a dielectric disposed between the semiconductor substrate and the gate conductor; a first terminal coupled to the gate conductor; and a second terminal coupled to the semiconductor substrate, wherein a breakdown of the dielectric causes electrical connections between regions of the gate conductor and regions of the active area including substantially near the STI boundary.