公开(公告)号：DE60106256D1

公开(公告)日：2004-11-11

申请号：DE60106256

申请日：2001-06-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KUNKEL GERHARD ,  BUTT SHAHID ,  RADENS CARL J

IPC: G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/00

Abstract: A dynamic random access memory is formed in a silicon chip in arrays of clusters, each of four cells in a single active area. Each active area is cross-shaped with vertical trenches at the four ends of the two crossbars. The central region of the active area where the two crossbars intersect serves as the common base region of the four transistors of the cluster. The top of the base region serves as a common drain for the four transistors and each transistor has a separate channel along the wall of its associated vertical trench that provides its storage capacitor. Each cluster includes a common bit line and four separate word-line contacts.

公开(公告)号：DE102004025108A1

公开(公告)日：2005-03-10

申请号：DE102004025108

申请日：2004-05-21

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： BRINTZINGER AXEL ,  TONTI WILLIAM ,  RADENS CARL J

IPC: H01L23/525 ,  H01L21/60 ,  H01L21/762

Abstract: Methods and apparatus for providing an antifuse are disclosed, where the antifuse includes a semiconductor substrate having an active area circumscribed by a shallow trench isolation (STI) boundary; a gate conductor disposed above the semiconductor substrate and overlying at least a portion of the STI boundary; a dielectric disposed between the semiconductor substrate and the gate conductor; a first terminal coupled to the gate conductor; and a second terminal coupled to the semiconductor substrate, wherein a breakdown of the dielectric causes electrical connections between regions of the gate conductor and regions of the active area including substantially near the STI boundary.

公开(公告)号：DE60106256T2

公开(公告)日：2005-10-20

申请号：DE60106256

申请日：2001-06-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： KUNKEL GERHARD ,  BUTT SHAHID ,  RADENS CARL J

IPC: G11C11/4097 ,  H01L21/8242 ,  H01L27/108 ,  G11C11/00

Abstract: A dynamic random access memory is formed in a silicon chip in arrays of clusters, each of four cells in a single active area. Each active area is cross-shaped with vertical trenches at the four ends of the two crossbars. The central region of the active area where the two crossbars intersect serves as the common base region of the four transistors of the cluster. The top of the base region serves as a common drain for the four transistors and each transistor has a separate channel along the wall of its associated vertical trench that provides its storage capacitor. Each cluster includes a common bit line and four separate word-line contacts.

公开(公告)号：EP1920493A4

公开(公告)日：2011-05-04

申请号：EP06802645

申请日：2006-08-30

Applicant: IBM

Inventor： HSU LOUIS C ,  CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  RADENS CARL J ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01H50/00 ,  H01P1/10

CPC classification number: H01H50/005 ,  H01H2050/007 ,  Y10T29/4902 ,  Y10T29/49105 ,  Y10T29/49147

公开(公告)号：EP1836726A4

公开(公告)日：2010-07-28

申请号：EP05852629

申请日：2005-12-02

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  DALTON TIMOTHY J ,  HSU LOUIS C ,  RADENS CARL J ,  STANDAERT THEODORUS E ,  WONG KEITH KWONG HON ,  YANG CHIH-CHAO

IPC: H01L21/4763

CPC classification number: H01L21/76852 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/76885 ,  H01L23/5226 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

公开(公告)号：EP2235744A4

公开(公告)日：2011-12-14

申请号：EP09704513

申请日：2009-01-15

Applicant: IBM

Inventor： CLEVENGER LAWRENCE A ,  DORIS BRUCE B ,  HUANG ELBERT E ,  PURUSHOTHAMAN SAMPATH ,  RADENS CARL J

IPC: H01L29/78 ,  H01L21/311 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L21/31144 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665 ,  H01L29/7833 ,  H01L29/7843

公开(公告)号：EP1812966A4

公开(公告)日：2010-07-14

申请号：EP05848854

申请日：2005-11-09

Applicant: IBM

Inventor： CHENG KANGGUO ,  RADENS CARL J

IPC: H01L21/8242

CPC classification number: H01L21/823807 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1087 ,  H01L27/10894 ,  H01L27/1203 ,  H01L27/1207

公开(公告)号：EP1977425A4

公开(公告)日：2009-04-29

申请号：EP07710032

申请日：2007-01-10

Applicant: IBM

Inventor： CHENG KANGGUO ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  RADENS CARL J ,  WANG GENG

IPC: G11C11/24 ,  H01L21/8242

CPC classification number: G11C8/16 ,  G11C11/405 ,  G11C11/4097 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10861

Abstract: An integrated circuit is provided which includes a memory having multiple ports per memory cell for accessing a data bit within each of a plurality of the memory cells. Such memory includes an array of memory cells in which each memory cell includes a plurality of capacitors (102) connected together as a unitary source of capacitance. A first access transistor (104) is coupled between a first one of the plurality of capacitors and a first bitline and a second access transistor (106) is coupled between a second one of the plurality of capacitors and a second bitline. In each memory cell, a gate of the first access transistor is connected to a first wordline and a gate of the second access transistor is connected to a second wordline.

公开(公告)号：JP2004088100A

公开(公告)日：2004-03-18

申请号：JP2003287161

申请日：2003-08-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KHAN BABAR A ,  RADENS CARL J ,  RAMACHANDRA DEIBAKARUNI

IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L27/10891 ,  H01L27/0207 ,  H01L27/10864

Abstract: PROBLEM TO BE SOLVED: To provide the structure of a built-in DRAM with a vertical device array and a bordered bit line contact, and a manufacturing method of the built-in DRAM.
SOLUTION: In an integrated circuit including a dynamic random access memory (DRAM), a DRAM cell has a storage capacitor in a deep trench, a transistor which has channels extending along side walls of the deep trench and a gate conductor in the deep trench, and a word line which makes contact with the gate conductor from above. The word line has a center line deviating from the center line of the gate conductor. The DRAM cell also has active regions extending from channels of the transistor and a bit line contact to the active regions, which are bordered by insulation spacers on side walls of the word line.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2001077321A

公开(公告)日：2001-03-23

申请号：JP2000220495

申请日：2000-07-21

Applicant: IBM

Inventor： GARY B BRONER ,  GAMBINO JEFFREY PETER ,  RADENS CARL J

IPC: B24B37/04 ,  H01L21/027 ,  H01L21/28 ,  H01L21/304 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/10

Abstract: PROBLEM TO BE SOLVED: To realize a process for manufacturing two kinds of different gate dielectric thicknesses by using a polysilicon mask and chemical mechanical polishing(CMP). SOLUTION: A thick gate dielectric 102 is grown on a substrate having a memory array area 201 and a logical device area 101, and a gate stack containing a first polysilicon layer 103 is formed on the dielectric 102. Then a thin gate dielectric 200 is formed on the substrate above the logical device area 101, and a second polysilicon layer 300 is formed in the logical device area 101. The thickness of the second polysilicon layer 300 is at least made to be equal to that of the gate stack in the memory array area 201. The structure is flattened by using chemical mechanical polishing(CMP), and the gate stack in the memory array area 201 and logical device area 101 is patterned.