Dual epitaxial layer for high voltage vertical conduction power mosfet devices

    公开(公告)号:AU5475100A

    公开(公告)日:2000-12-28

    申请号:AU5475100

    申请日:2000-06-08

    Abstract: The epitaxial silicon junction receiving layer of a power semiconductor device is formed of upper and lower layers. The lower layer has a resistivity of more than that of the upper layer and a thickness of more than that of the upper layer. The total thickness of the two layers is less than that of a single epitaxial layer that would be used for the same blocking voltage. P-N junctions are formed in the upper layer to define a vertical conduction power MOSFET device. The on-resistance is reduced more than 10% without any blocking voltage reduce. The upper epitaxial layer can be either by direct second layer deposition or by ion implantation of a uniform epitaxial layer followed by a driving process.

    14.
    发明专利
    未知

    公开(公告)号:FR2739976B1

    公开(公告)日:1999-04-02

    申请号:FR9612435

    申请日:1996-10-11

    Abstract: A termination structure for semiconductor devices and a process for fabricating the termination structure are described which prevent device breakdown at the peripheries of the device. The termination structure includes a polysilicon field plate located atop a portion of a field oxide region and which, preferably, overlays a portion of the base region. The field plate may also extend slightly over the edge of the field oxide to square off the field oxide taper. The termination structure occupies minimal surface area of the chip and is fabricated without requiring additional masking steps.

    15.
    发明专利
    未知

    公开(公告)号:IT1285780B1

    公开(公告)日:1998-06-18

    申请号:ITMI962099

    申请日:1996-10-10

    Abstract: A termination structure for semiconductor devices and a process for fabricating the termination structure are described which prevent device breakdown at the peripheries of the device. The termination structure includes a polysilicon field plate located atop a portion of a field oxide region and which, preferably, overlays a portion of the base region. The field plate may also extend slightly over the edge of the field oxide to square off the field oxide taper. The termination structure occupies minimal surface area of the chip and is fabricated without requiring additional masking steps.

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