公开(公告)号：GB2476142B

公开(公告)日：2014-06-25

申请号：GB201018116

申请日：2010-10-26

Applicant: INTEL CORP

Inventor： BAINS KULJIT S ,  ZIMMERMAN DAVID J ,  BRZEZINSKI DENIS W ,  WILLIAMS MICHAEL ,  HALBERT JOHN B

IPC: G06F11/10

公开(公告)号：GB2446971A

公开(公告)日：2008-08-27

申请号：GB0806199

申请日：2006-12-08

Applicant: INTEL CORP

Inventor： BAINS KULJIT ,  HALBERT JOHN B ,  OSBORNE RANDY

IPC: G06F13/16

Abstract: In some embodiments, a chip includes first and second bank sets, a first data port mapped to the first bank set, and a second data port mapped to the second bank set. Other embodiments are described.

公开(公告)号：GB2502700B

公开(公告)日：2014-06-11

申请号：GB201308311

申请日：2010-10-26

Applicant: INTEL CORP

Inventor： BAINS KULJIT S ,  ZIMMERMAN DAVID J ,  BRZEZINSKI DENIS W ,  WILLIAMS MICHAEL ,  HALBERT JOHN B

IPC: G06F11/10

公开(公告)号：GB2502700A

公开(公告)日：2013-12-04

申请号：GB201308311

申请日：2010-10-26

Applicant: INTEL CORP

Inventor： BAINS KULJIT S ,  ZIMMERMAN DAVID J ,  BRZEZINSKI DENIS W ,  WILLIAMS MICHAEL ,  HALBERT JOHN B

IPC: G06F11/10

Abstract: A memory controller (110) includes a logic unit (112) to provide a command, and a parity bit signal (14) associated with the command, to one or more memory devices (120). The logic unit is further to detect 505 whether an indication of a parity error of the command is received. The logic unit is further adapted to, responsive to a detection of the indication of the parity error: wait 525 until all of one or more commands sent before the command with the parity error to the one or more memory devices have completed execution; send (625, 630) a pre-charge command and a refresh command to all memory devices, and determine which one of the one or more memory devices has received the command with the parity error. In other embodiments, the controller includes logic to detect whether an indication of a cyclic redundancy check (CRC) error and the one or more memory devices (120) includes a mode register (122) and error-handing logic (124) that asserts a continuous alert signal responsive to a parity error and a pulse responsive to a CRC error.

公开(公告)号：DE602004029192D1

公开(公告)日：2010-10-28

申请号：DE602004029192

申请日：2004-12-23

Applicant: INTEL CORP

Inventor： HALBERT JOHN B ,  ELLIS ROBERT M ,  BAINS KULJIT S ,  FREEMAN CHRIS B

IPC: G11C7/10 ,  G11C11/4096

公开(公告)号：GB2513233A

公开(公告)日：2014-10-22

申请号：GB201402999

申请日：2010-10-26

Applicant: INTEL CORP

Inventor： BAINS KULJIT S ,  ZIMMERMAN DAVID J ,  BRZEZINSKI DENIS W ,  WILLIAMS MICHAEL ,  HALBERT JOHN B

IPC: G06F11/10

Abstract: A memory system 100 includes memory controller 110 having error handling logic 112 to compute parity of address signal bits and command signal bits of a command to be sent to RAM memory module 120 and being configured to provide a parity bit signal 140 based on said computed parity when sending the command to memory module 120. Memory module 120 has mode register 122 and error handling logic 124 adapted to detect if the received command has any command/address (C/A) parity error or any cyclic redundancy check (CRC) error. On detection of a parity error, the memory module ignores the received command, stores the command bits and addresses bits of the command in the mode register, and asserts an error indication signal, e.g. a continuous indication signal, to the memory controller. When a CRC error in the command is detected, memory module asserts an indication signal, e.g. for a number of pulses, to the memory controller. Memory controller is further configured to determine from said indication signal whether a parity or a CRC error is present in the command and to perform a recovery mechanism to recover from the parity or CRC error.

公开(公告)号：DE102010053281A1

公开(公告)日：2011-08-04

申请号：DE102010053281

申请日：2010-12-02

Applicant: INTEL CORP

Inventor： BAINS KULJIT S ,  ZIMMERMAN DAVID J ,  BRZEZINSKI DENNIS W ,  WILLIAMS MICHAEL ,  HALBERT JOHN B

IPC: G06F11/10 ,  G06F9/30

Abstract: Ein Verfahren und System zur Fehlerbehandlung bei einem Speichergerät. Bei einer erfindungsgemäßen Ausführungsform kann das Speichergerät Befehls- und Adress-Paritätsfehler und Fehler bei der zyklischen Redundanzprüfung verarbeiten. Bei einer erfindunen, ob ein empfangener Befehl irgendwelche Paritätsfehler aufweist, indem bestimmt wird, ob die Befehlsbits oder die Adressbits des empfangenen Befehls irgendwelche Paritätsfehler aufweisen. Wird ein Paritätsfehler oder Fehler bei der zyklischen Redundanzprüfung bei dem empfangenen Befehl erkannt, wird ein Fehlerverarbeitungsmechanismus ausgelöst, um den falschen Befehl zu beheben.

公开(公告)号：GB2446971B

公开(公告)日：2010-11-24

申请号：GB0806199

申请日：2006-12-08

Applicant: INTEL CORP

Inventor： BAINS KULJIT ,  HALBERT JOHN B ,  OSBORNE RANDY

IPC: G06F13/16

公开(公告)号：DE112006003503T5

公开(公告)日：2008-10-30

申请号：DE112006003503

申请日：2006-12-08

Applicant: INTEL CORP

Inventor： BAINS KULJIT S ,  HALBERT JOHN B ,  OSBORNE RANDY B

IPC: G06F13/16

公开(公告)号：EP3198605A4

公开(公告)日：2018-05-23

申请号：EP15844842

申请日：2015-08-19

Applicant: INTEL CORP

Inventor： HALBERT JOHN B ,  CHRISTENSON BRUCE A ,  BAINS KULJIT S

IPC: G11C11/4096 ,  G06F13/16 ,  G06F21/79 ,  G11C7/10 ,  G11C11/401 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4094

CPC classification number: G11C7/1072 ,  G06F13/1668 ,  G06F13/1689 ,  G06F21/79 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1063 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4094 ,  Y02D10/14

Abstract: Techniques and mechanisms for exchanging information between a memory controller and a memory device. In an embodiment, a memory controller receives information indicating for a memory device a threshold number of pending consolidated activation commands to access that memory device. The threshold number indicated by the information is less than a theoretical maximum number of pending consolidated activation commands, the theoretical maximum number defined based on timing parameters of the memory device. In another embodiment, the memory controller limits communication of consolidated activation commands to the memory device based on the information indicating the threshold number.