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    Primitives to enhance thread-level speculation
    11.
    发明专利
    Primitives to enhance thread-level speculation 审中-公开
    提高螺纹水准仪的主要原则

    公开(公告)号：JP2013168168A

    公开(公告)日：2013-08-29

    申请号：JP2013083679

    申请日：2013-04-12

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： QUINN JACOBSON ,  WANG HONG ,  JOHN SHEN ,  CHINYA GOTHAM ,  HAMMARLUND PER ,  ZOU SHANG ,  BIGBEE BRYANT ,  SHIVNANDAN KAUSHIK

    IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/52 ,  G06F12/00

    CPC classification number: G06F9/526 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861

    Abstract: PROBLEM TO BE SOLVED: To provide a processor which may include an address monitor table and an atomic update table to support speculative threading.SOLUTION: The processor may also include one or more registers to maintain a state associated with execution of speculative threads. The processor may support one or more of the following primitives: an instruction for writing to a register of the state, an instruction for triggering commitment of buffered memory updates, an instruction for reading a status register of the state, and/or an instruction for clearing one of the state bits associated with trap/exception/interrupt handling. Other embodiments are also described and claimed.

    Abstract translation: 要解决的问题：提供一种处理器，其可以包括地址监视表和原子更新表以支持推测性线程。解决方案：处理器还可以包括一个或多个寄存器以维持与推测线程的执行相关联的状态。 处理器可以支持以下一个或多个原语：用于写入状态寄存器的指令，用于触发缓冲存储器更新的承诺的指令，用于读取状态的状态寄存器的指令和/或用于 清除与陷阱/异常/中断处理相关联的状态位之一。 还描述和要求保护其他实施例。

    Instruction set architecture-based inter-sequencer communication with heterogeneous resource
    12.
    发明专利
    Instruction set architecture-based inter-sequencer communication with heterogeneous resource 审中-公开
    具有异构资源的基于指令集架构的串行间通信

    公开(公告)号：JP2011146077A

    公开(公告)日：2011-07-28

    申请号：JP2011101385

    申请日：2011-04-28

    Applicant: Intel Corp ,  インテル コーポレイション

    Inventor： WANG HONG ,  SHEN JOHN ,  ZHANG HONG ,  HANKINS RICHARD ,  HAMMARLUND PER ,  RODGERS DION ,  CHINYA GAUTHAM ,  PATEL BAIJU ,  KAUSHIK SHIV ,  BIGBEE BRYANT ,  SHEAFFER GAD ,  TALGAM YOAV ,  YOSEF YUVAL ,  HELD JAMES P

    IPC: G06F9/38

    CPC classification number: G06F9/30145 ,  G06F9/30 ,  G06F9/30181 ,  G06F9/3877 ,  G06F9/3879 ,  G06T1/20

    Abstract: PROBLEM TO BE SOLVED: To provide a method, a device, and a system for performing effective communication between instruction set architecture-based sequencers having heterogeneous resources. SOLUTION: The method includes: a step in which a first instruction sequencer is connected from a user-level application via the first instruction sequencer and a request is directly communicated to an accelerator having a heterogeneous resource with respect to the instruction sequencer; a step of providing the accelerator with the request via an exoskeleton related to the accelerator; and a step of performing a first function in parallel to a second function in the first instruction sequencer in response to the request in the accelerator. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于在具有异构资源的指令集体系结构的定序器之间执行有效通信的方法，设备和系统。 该方法包括：第一指令定序器经由第一指令定序器从用户级应用连接并且请求直接传送到相对于指令定序器具有异构资源的加速器的步骤; 通过与加速器有关的外骨骼提供加速器请求的步骤; 以及响应于加速器中的请求，在第一指令定序器中执行与第二功能并行的第一功能的步骤。 版权所有（C）2011，JPO＆INPIT

    Mechanism for instruction set based on thread execution on plurality of instruction sequencers
    13.
    发明专利
    Mechanism for instruction set based on thread execution on plurality of instruction sequencers 有权
    基于指令序列的多项式执行指令集的机制

    公开(公告)号：JP2011023032A

    公开(公告)日：2011-02-03

    申请号：JP2010204922

    申请日：2010-09-13

    Applicant: Intel Corp ,  インテル・コーポレーション

    Inventor： WANG HONG ,  SHEN JOHN ,  GROCHOWSKI ED ,  HELD JAMES PAUL ,  BIGBEE BRYANT ,  KAUSHIK SHIVNANDAN D ,  CHINYA GAUTHAM ,  ZOU XIANG ,  HAMMARLUND PER ,  TIAN XINMIN ,  AGGARWAL ANIL ,  RODGERS SCOTT DION ,  PATEL BAIJU V ,  RICHARD HANKINS

    IPC: G06F9/46 ,  G06F9/38

    CPC classification number: G06F9/3851 ,  G06F9/4843

    Abstract: PROBLEM TO BE SOLVED: To provide a mechanism for scheduling user-level threads so that the user-level threads can be executed on a processor that is not directly managed by an OS.
    SOLUTION: User-level threads on a first instruction sequencer are managed in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the second instruction sequencer and contains one or more user level instructions. A first user level instruction has at least (1) a field that makes reference to one or more instruction sequencers or (2) implicitly references with a pointer to a code that specifically addresses one or more instruction sequencers when the code is executed.
    COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供一种用于调度用户级线程的机制，使得可以在不由OS直接管理的处理器上执行用户级线程。 解决方案：响应于在应用级程序的控制下的第二指令定序器上执行用户级指令来管理第一指令定序器上的用户级线程。 在第二指令定序器上运行第一用户级线程并且包含一个或多个用户级指令。 第一用户级指令至少具有（1）引用一个或多个指令定序器的字段，或（2）隐含地引用指向代码执行时特定地址一个或多个指令定序器的代码的指针。 版权所有（C）2011，JPO＆INPIT

    Compare and exchange operation using sleep-wakeup mechanism
    15.
    发明专利
    Compare and exchange operation using sleep-wakeup mechanism 审中-公开
    使用睡眠唤醒机制的比较和交换操作

    公开(公告)号：JP2006031691A

    公开(公告)日：2006-02-02

    申请号：JP2005178287

    申请日：2005-06-17

    Applicant: Intel Corp ,  インテル・コーポレーション

    Inventor： SAHA BRATIN ,  MERTEN MATTHEW ,  HAMMARLUND PER

    IPC: G06F9/52 ,  G06F1/32 ,  G06F9/38 ,  G06F9/46 ,  G06F12/00

    CPC classification number: G06F9/30021 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3857 ,  G06F9/526 ,  G06F2209/521

    Abstract: PROBLEM TO BE SOLVED: To improve bottlenecking of resources, waste of memory bandwidth, compute bandwidth, microarchitectural resources and power which are generated when waiting for lock of a share resource between processors (or threads) to become available.
    SOLUTION: A method, apparatus and system are provided for performing compare and exchange operations using a sleep-wakeup mechanism. According to one embodiment, an instruction at a processor is executed to help acquire a lock on behalf of the processor. If the lock is unavailable to be acquired by the processor, the instruction is put to sleep until an event has occurred.
    COPYRIGHT: (C)2006,JPO&NCIPI

    Abstract translation: 要解决的问题：为了改善资源的瓶颈，浪费存储器带宽，计算带宽，微架构资源和在等待处理器（或线程）之间的共享资源锁定可用时生成的功率。 解决方案：提供了一种使用睡眠唤醒机制进行比较和交换操作的方法，装置和系统。 根据一个实施例，执行处理器处的指令以帮助代表处理器获取锁定。 如果锁不能由处理器获取，则指令将进入休眠状态，直到发生事件为止。 版权所有（C）2006，JPO＆NCIPI

    SYNCHRONIZATION OF INTERRUPT PROCESSING TO REDUCE POWER CONSUMPTION
    16.
    发明申请
    SYNCHRONIZATION OF INTERRUPT PROCESSING TO REDUCE POWER CONSUMPTION 审中-公开
    中断处理同步降低功耗

    公开(公告)号：WO2015143594A8

    公开(公告)日：2016-08-04

    申请号：PCT/CN2014073926

    申请日：2014-03-24

    Applicant: INTEL CORP ,  LOH THIAM WAH ,  CHINYA GAUTHAM N ,  HAMMARLUND PER ,  FORTAS REZA ,  WANG HONG ,  SUN HUAJIN

    Inventor： LOH THIAM WAH ,  CHINYA GAUTHAM N ,  HAMMARLUND PER ,  FORTAS REZA ,  WANG HONG ,  SUN HUAJIN

    IPC: G06F13/24

    CPC classification number: G06F13/24 ,  G06F2213/2404 ,  G06F2213/2406 ,  Y02D10/14

    Abstract: A processor is disclosed and includes at least one core including a first core, and interrupt delay logic. The interrupt delay logic is to receive a first interrupt at a first time and delay the first interrupt from being processed by a first time delay that begins at the first time,unless the first interrupt is pending at a second time when a second interrupt is processed by the first core. If the first interrupt is pending at the second time,the interrupt delay logic is to indicate to the first core to begin to process the first interrupt prior to completion of the first time delay. Other embodiments are disclosed and claimed.

    Abstract translation: 公开了一种处理器，并且包括至少一个包括第一核心和中断延迟逻辑的核心。 中断延迟逻辑是在第一时间接收第一个中断，并延迟第一个中断从第一个时间开始的第一个时间延迟处理，除非第一个中断在第二个中断处理时处于待机状态 由第一核心。 如果第二次中断第一次中断，中断延迟逻辑将在第一个时间延迟完成之前指示第一个内核开始处理第一个中断。 公开和要求保护其他实施例。

    METHOD AND APPARATUS FOR SPECULATIVE EXECUTION OF UNCONTENDED LOCK INSTRUCTIONS
    17.
    发明申请
    METHOD AND APPARATUS FOR SPECULATIVE EXECUTION OF UNCONTENDED LOCK INSTRUCTIONS 审中-公开
    用于未执行的锁定指令的执行的方法和装置

    公开(公告)号：WO2006012103A2

    公开(公告)日：2006-02-02

    申请号：PCT/US2005021838

    申请日：2005-06-17

    Applicant: INTEL CORP ,  SAHA BRATIN ,  MERTEN MATTHEW C ,  HAMMARLUND PER

    Inventor： SAHA BRATIN ,  MERTEN MATTHEW C ,  HAMMARLUND PER

    IPC: G06F9/00

    CPC classification number: G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3842

    Abstract: A method and apparatus for executing lock instructions speculatively in an out-of-order processor are disclosed. In one embodiment, a prediction is made whether a given lock instruction will actually be contended. If not, then the lock instruction may be treated as having a normal load micro-operation which may be speculatively executed. Monitor logic may look for indications that the lock instruction is actually contended. If no such indications are found, the speculative load micro-operation and other micro-operations corresponding to the lock instruction may retire. However, if such indications are in fact found, the lock instruction may be restarted, and the prediction mechanism may be updated.

    Abstract translation: 公开了一种在无序处理器中推测性地执行锁定指令的方法和设备。 在一个实施例中，预测给定的锁定指令是否实际上将被争用。 如果不是，则锁定指令可被视为具有可被推测执行的正常加载微操作。 监视逻辑可以查找锁指令实际上是否存在争用的指示。 如果没有找到这样的指示，则可以撤销对应于锁定指令的推测加载微操作和其他微操作。 但是，如果实际上发现了这样的指示，那么可以重新开始锁定指令，并且可以更新预测机制。

    DECOUPLING THE NUMBER OF LOGICAL THREADS FROM THE NUMBER OF SIMULTANEOUS PHYSICAL THREADS IN A PROCESSOR
    18.
    发明申请
    DECOUPLING THE NUMBER OF LOGICAL THREADS FROM THE NUMBER OF SIMULTANEOUS PHYSICAL THREADS IN A PROCESSOR 审中-公开
    从处理器中同时存在的多个物理线程中去除逻辑线程的数量

    公开(公告)号：WO2006057647A3

    公开(公告)日：2006-07-20

    申请号：PCT/US2004043036

    申请日：2004-12-20

    Applicant: INTEL CORP ,  HAMMARLUND PER ,  FARCY ALEXANDRE ,  MARDEN MORRIS ,  CARMEAN DOUGLAS ,  MICHAUD PIERRE ,  HINTON ROBERT

    Inventor： HAMMARLUND PER ,  FARCY ALEXANDRE ,  MARDEN MORRIS ,  CARMEAN DOUGLAS ,  MICHAUD PIERRE ,  HINTON ROBERT ,  JOURDAN STEPHAN

    IPC: G06F9/46 ,  G06F9/48 ,  G06F11/00

    CPC classification number: G06F9/485 ,  G06F9/3851

    Abstract: Systems and methods of managing threads provide for supporting a plurality of logical threads with a plurality of simultaneous physical threads in which the number of logical threads may be greater than or less than the number of physical threads. In one approach, each of the plurality of logical threads is maintained in one of a wait state, an active state, a drain state, and a stall state. A state machine and hardware sequencer can be used to transition the logical threads between states based on triggering events and whether or not an interruptible point has been encountered in the logical threads. The logical threads are scheduled on the physical threads to meet, for example, priority, performance or fairness goals. It is also possible to specify the resources that are available to each logical thread in order to meet these and other, goals. In one example, a single. logical thread can speculatively use more than one physical thread, pending a selection of which physical thread should be committed.

    Abstract translation: 管理线程的系统和方法提供支持具有多个同时物理线程的多个逻辑线程，其中逻辑线程的数量可以大于或小于物理线程的数量。 在一种方法中，多个逻辑线程中的每一个保持在等待状态，活动状态，排出状态和停转状态之一。 可以使用状态机和硬件定序器基于触发事件以及逻辑线程中是否遇到可中断点来转换状态之间的逻辑线程。 逻辑线程在物理线程上进行调度，以满足例如优先级，性能或公平目标。 也可以指定每个逻辑线程可用的资源，以满足这些和其他目标。 在一个例子中，一个单一的。 逻辑线程可以推测性地使用多个物理线程，等待选择哪个物理线程应该提交。

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