公开(公告)号：GB2404119A

公开(公告)日：2005-01-19

申请号：GB0423209

申请日：2002-03-01

Applicant: INTEL CORP

Inventor： KARDACH JAMES P ,  SCHIFFER JEFFREY

IPC: G06F1/16 ,  H04L12/28 ,  H04L12/56 ,  H04L29/06 ,  H04L29/08

Abstract: A method of operating a radio module partitioned to meet government regulations with protocol flexibility operates the module in accordance with a first wireless communication protocol during a first period of time, the radio module meeting with LMA approval by the FCC or similar type approval relevant to the U.K. independent of the computer system. The method further enables the computer system to operate the radio module in accordance with a second wireless communication protocol during a second period of time.

公开(公告)号：HK1061762A1

公开(公告)日：2004-09-30

申请号：HK04104565

申请日：2004-06-25

Applicant: INTEL CORP

Inventor： KARDACH JAMES P ,  CHINN GORDON ,  DURRANT RANDY ,  RAJAMANI KRISHNAN ,  MONROE ROBERT L

IPC: H04L12/28 ,  H04W20090101 ,  H04W88/06

Abstract: Methods and apparatus are disclosed for communicating via a radio channel to reduce radio frequency (RF) interference between transceiver systems within an electronic device.

公开(公告)号：GB2393363A

公开(公告)日：2004-03-24

申请号：GB0325166

申请日：2002-03-01

Applicant: INTEL CORP

Inventor： KARDACH JAMES P ,  SCHIFFER JEFFREY

IPC: G06F1/16 ,  H04L12/28 ,  H04L12/56 ,  H04L29/06 ,  H04L29/08

Abstract: A radio module that meets FCC Limited Modular Approval including a wireless transceiver and a low-level baseband controller. Only a portion of the baseband associated with a wireless communication protocol is contained within the controller. The remainder of the baseband may be contained within a host computer system to which the module may be coupled such that, for one embodiment, the module may be selectively operated in accordance with one of multiple wireless communication protocols.

公开(公告)号：HK1027403A1

公开(公告)日：2001-01-12

申请号：HK00105429

申请日：2000-08-30

Applicant: INTEL CORP

Inventor： CHO SUNG-SOO ,  BRYANT DIANE M ,  KARDACH JAMES P ,  DENG FENG

IPC: G06F13/12 ,  G06F1/16 ,  G06F3/00 ,  G06F13/40 ,  G06F

Abstract: Prior art quiet docking and undocking methods used an interface that was located within the notebook computer, thus adding to the cost, complexity, weight, and power consumption of the notebook computer. The present invention provides for an apparatus for quiet docking of a notebook computer to a docking station, including interface circuitry located within the docking station. The interface detects when the notebook computer has been inserted within the docking station, and correspondingly enables a switch such that a common system bus is coupled between the notebook computer and the docking station. The interface also generates events to allow a software routine to configure the notebook computer and docking station without prior user intervention. The interface also includes circuitry to detect an undock request, and correspondingly undock the computer such that a transaction occurring on the system bus is not affected.

公开(公告)号：HK165095A

公开(公告)日：1995-11-03

申请号：HK165095

申请日：1995-10-26

Applicant: INTEL CORP

Inventor： KARDACH JAMES P ,  NGUYEN CAU

IPC: G06F9/46 ,  G06F9/48 ,  G06F12/14

Abstract: A dedicated memory area is provided on a microprocessor system for storing a customizable system interrupt service routine, and processor state data at the time of interruption. The dedicated memory area is normally not mapped as part of the main memory space, thereby keep it inaccessible to the operating system and applications. An unmaskable system supervisor interrupt having higher priority than all other maskable and unmaskable interrupts is added to the CPU interrupts. The extended memory addressing limits are overridden when the CPU is interrupted by this added interrupt. A RESUME instruction is added to the CPU instructions to provide recovery of the CPU to the state before it was interrupted. The extended memory addressing limits are restored when the CPU is restored by the RESUME instruction. As a result, a system integrator or OEM may provide transparent system level interrupts with integrated extended memory addressing that will operate reliably in any operating environment, and be able to address the entire physical address space and have access to all system resources in a stand alone manner during the interrupt.

公开(公告)号：DE19681716B4

公开(公告)日：2004-02-26

申请号：DE19681716

申请日：1996-12-27

Applicant: INTEL CORP

Inventor： KARDACH JAMES P ,  CHUNG CHIH-HUNG ,  ZILLER JASON

IPC: G06F1/32

Abstract: A computer system for monitoring the activity of a bus controller of a processor and responsive thereto for controlling the power consumption of a target controller such as a memory controller coupled to the bus controller. The computer system includes a bus, a processor having a bus controller coupled to the bus, and a bus activity monitor, coupled to the bus controller, generating a bus activity signal indicative of activity in the bus controller. The computer system also includes a target controller, coupled to the bus controller, for controlling the exchange of information between the processor and a target circuit. The target controller has an input for receiving a sequencing signal. The computer system additionally includes a power management circuit for controlling a power consumption of the target controller. The power management circuit has an input for receiving the bus activity signal and, an output for generating the sequencing signal in response to the bus activity signal.

公开(公告)号：DE69522595D1

公开(公告)日：2001-10-18

申请号：DE69522595

申请日：1995-01-06

Applicant: INTEL CORP

Inventor： RABE JEFFREY L ,  BHATT AJAY V ,  BOGIN ZOHAR ,  KARDACH JAMES P ,  SHAH NILESH V

IPC: G06F1/32

Abstract: A power consumption controller is described which switches a computer system between a fully operational mode and a responsive blow power mode. The computer system in the responsive low power mode is responsive to a computer network signal of a specified minimum duration.

公开(公告)号：GB2340973B

公开(公告)日：2001-09-12

申请号：GB9911695

申请日：1997-09-29

Applicant: INTEL CORP

Inventor： CHO SUNG-SOO ,  BRYANT DIANE M ,  KARDACH JAMES P ,  DENG FENG

IPC: G06F13/12 ,  G06F1/16 ,  G06F3/00 ,  G06F13/40

Abstract: Prior art quiet docking and undocking methods used an interface that was located within the notebook computer, thus adding to the cost, complexity, weight, and power consumption of the notebook computer. The present invention provides for an apparatus for quiet docking of a notebook computer to a docking station, including interface circuitry located within the docking station. The interface detects when the notebook computer has been inserted within the docking station, and correspondingly enables a switch such that a common system bus is coupled between the notebook computer and the docking station. The interface also generates events to allow a software routine to configure the notebook computer and docking station without prior user intervention. The interface also includes circuitry to detect an undock request, and correspondingly undock the computer such that a transaction occurring on the system bus is not affected.

公开(公告)号：GB2322212B

公开(公告)日：2000-06-14

申请号：GB9812477

申请日：1996-12-27

Applicant: INTEL CORP

Inventor： KARDACH JAMES P ,  CHUNG CHIH-HUNG ,  ZILLER JASON

IPC: G06F1/32 ,  G06F11/30

Abstract: A computer system for monitoring the activity of a bus controller of a processor and responsive thereto for controlling the power consumption of a target controller such as a memory controller coupled to the bus controller. The computer system includes a bus, a processor having a bus controller coupled to the bus, and a bus activity monitor, coupled to the bus controller, generating a bus activity signal indicative of activity in the bus controller. The computer system also includes a target controller, coupled to the bus controller, for controlling the exchange of information between the processor and a target circuit. The target controller has an input for receiving a sequencing signal. The computer system additionally includes a power management circuit for controlling a power consumption of the target controller. The power management circuit has an input for receiving the bus activity signal and, an output for generating the sequencing signal in response to the bus activity signal.

公开(公告)号：DE19782133T1

公开(公告)日：1999-10-28

申请号：DE19782133

申请日：1997-09-29

Applicant: INTEL CORP

Inventor： CHO SUNG-SOO ,  BRYANT DIANE M ,  KARDACH JAMES P ,  DENG FENG

IPC: G06F13/12 ,  G06F1/16 ,  G06F3/00 ,  G06F13/40 ,  H01J3/00

Abstract: Prior art quiet docking and undocking methods used an interface that was located within the notebook computer, thus adding to the cost, complexity, weight, and power consumption of the notebook computer. The present invention provides for an apparatus for quiet docking of a notebook computer to a docking station, including interface circuitry located within the docking station. The interface detects when the notebook computer has been inserted within the docking station, and correspondingly enables a switch such that a common system bus is coupled between the notebook computer and the docking station. The interface also generates events to allow a software routine to configure the notebook computer and docking station without prior user intervention. The interface also includes circuitry to detect an undock request, and correspondingly undock the computer such that a transaction occurring on the system bus is not affected.