公开(公告)号：JP2010156970A

公开(公告)日：2010-07-15

申请号：JP2009287634

申请日：2009-12-18

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： KWA SEH W ,  KARDACH JAMES P

IPC: G09G5/00 ,  G06F3/153

CPC classification number: G09G5/36 ,  G09G5/003 ,  G09G2320/103 ,  G09G2330/021 ,  G09G2360/06 ,  G09G2360/10 ,  G09G2360/18

Abstract: PROBLEM TO BE SOLVED: To solve such a problem that power incurred becomes wasteful when the system is idle (e.g., while the image on the display does not change for a given time period).
SOLUTION: A technique that relates to hybrid graphics display power management is described. Data corresponding to one or more image frames of a video stream are stored in a local frame buffer. A display device (e.g., an LCD) may then be driven based on the stored data in the local frame buffer or a video stream from a graphics controller.
COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：为了解决当系统空闲时（例如，当显示器上的图像在给定时间段内没有变化时）所产生的功率变得浪费的这样一个问题。 解决方案：描述了一种与混合图形显示电源管理相关的技术。 对应于视频流的一个或多个图像帧的数据被存储在本地帧缓冲器中。 然后可以基于本地帧缓冲器中存储的数据或来自图形控制器的视频流来驱动显示设备（例如，LCD）。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：WO2007002921A2

公开(公告)日：2007-01-04

申请号：PCT/US2006025774

申请日：2006-06-29

Applicant: INTEL CORP ,  KARDACH JAMES P ,  WILLIAMS DAVID ,  BHOWMIK ACHINTYA K ,  COOPER BARNES

Inventor： KARDACH JAMES P ,  WILLIAMS DAVID ,  BHOWMIK ACHINTYA K ,  COOPER BARNES

IPC: G09G3/36 ,  G09G5/36

CPC classification number: G09G5/006 ,  G09G3/3648 ,  G09G5/363 ,  G09G2330/021 ,  G09G2340/0435

Abstract: Apparatus and systems, as well as methods and articles, may operate to update video display pixels. A video display bus can communicate data to a video display according to specified clock frequencies and a refresh time period. Power conservation can be enhanced by adjusting the specified clock frequencies and/or refresh time period to provide idle time on the video display bus.

Abstract translation: 设备和系统以及方法和物品可以操作来更新视频显示像素。 视频显示总线可以根据指定的时钟频率和刷新时间周期将数据传送到视频显示器。 可以通过调整指定的时钟频率和/或刷新时间来提高功率节省，从而在视频显示总线上提供空闲时间。

公开(公告)号：DE112013006266B4

公开(公告)日：2018-04-19

申请号：DE112013006266

申请日：2013-06-25

Applicant: INTEL CORP

Inventor： KARDACH JAMES P ,  MACDONALD KIRSTY ,  GIBSON PETER

IPC: G11B19/28

Abstract: Controller (600), der Folgendes umfasst:Spulentreiber eines Controllers (611), um Spulen (621) eines elektrischen Motors (623) anzutreiben, um einen Permanentmagneten (622) eines Motors zu drehen, wobei der Permanentmagnet (622) mechanisch an Plattenmedien (626) gekoppelt ist, um die Plattenmedien zu drehen, undeine Logik, die den Controller (600) veranlasst:die Spulen (621) elektrisch anzutreiben, um zu bewirken, dass sich die Plattenmedien (626) mit einer gewählten normalen Drehzahl drehen;aufzuhören, die Spulen (621) elektrisch anzutreiben, um den Plattenmedien (626) zu ermöglichen, sich frei zu drehen;Signale zu überwachen, die von den Spulen (621) empfangen werden, um eine aktuelle Drehzahl der Plattenmedien (626) zu überwachen, wenn sich die Plattenmedien (626) frei drehen, unddas elektrische Antreiben der Spulen (621) wiederaufzunehmen, um die Plattenmedien (626) zu drehen, als Reaktion darauf, dass die Drehzahl der Plattenmedien (626) auf einen unteren Schwellenwert der Drehzahl gefallen ist, der gewählt ist, eine von Null verschiedene Drehzahl und kleiner als die normale Drehzahl zu sein, undnach Erreichen eines oberen Schwellenwertes der Drehzahl aufzuhören die Spulen (621) elektrisch anzutreiben, wobei der obere Schwellenwert der Drehzahl eine Drehzahl zwischen dem unteren Schwellenwert der Drehzahl und der normalen Drehzahl ist.

公开(公告)号：GB2340973A

公开(公告)日：2000-03-01

申请号：GB9911695

申请日：1997-09-29

Applicant: INTEL CORP

Inventor： CHO SUNG-SOO ,  BRYANT DIANE M ,  KARDACH JAMES P ,  DENG FENG

IPC: G06F13/12 ,  G06F1/16 ,  G06F3/00 ,  G06F13/40

Abstract: Prior art quiet docking and undocking method used an interface that was located within notebook computer (10), thus adding to the cost, complexity, weight, and power consumption of the notebook computer (10). The present invention provides for an apparatus for quiet docking of a notebook computer (10) to a docking station (11), including interface circuitry located within the docking station. The interface detects when the notebook computer (10) has been inserted within the docking station (11), and correspondingly enables a switch such that a common system bus is coupled between the notebook computer (10) and docking station (11). The interface also generates events to allow a software routine to configure the notebook computer (10) and docking station (11) without prior user intervention. The interface also includes cicuitry to detect an undock request, and correspondingly undock the computer such that a transaction occurring on the system bus is not affected.

公开(公告)号：HK1015902A1

公开(公告)日：1999-10-22

申请号：HK99100682

申请日：1999-02-19

Applicant: INTEL CORP

Inventor： KARDACH JAMES P ,  CHUNG CHIH-HUNG ,  ZILLER JASON

IPC: G06F1/32 ,  G06F

Abstract: A computer system for monitoring the activity of a bus controller of a processor and responsive thereto for controlling the power consumption of a target controller such as a memory controller coupled to the bus controller. The computer system includes a bus, a processor having a bus controller coupled to the bus, and a bus activity monitor, coupled to the bus controller, generating a bus activity signal indicative of activity in the bus controller. The computer system also includes a target controller, coupled to the bus controller, for controlling the exchange of information between the processor and a target circuit. The target controller has an input for receiving a sequencing signal. The computer system additionally includes a power management circuit for controlling a power consumption of the target controller. The power management circuit has an input for receiving the bus activity signal and, an output for generating the sequencing signal in response to the bus activity signal.

公开(公告)号：GB2322212A

公开(公告)日：1998-08-19

申请号：GB9812477

申请日：1996-12-27

Applicant: INTEL CORP

Inventor： KARDACH JAMES P ,  CHUNG CHIH-HUNG ,  ZILLER JASON

IPC: G06F1/32

Abstract: A computer system is provided for monitoring the activity of a bus controller (208) of a processor (204) and responsive thereto for controlling the power consumption of a target controller such as memory controller (216) coupled to the bus controller (208). The computer system includes a bus (202), a processor (204), and a bus activity monitor (212) for generating a bus activity signal indicative of activity in the bus controller (208). The target controller (memory controller (216)) controls the exchange of information between the processor (204) and a target circuit such as DRAM (218). The target controller (216) has an input (215) for receiving a sequencing signal. The computer system additionally includes a power management circuit (220) for controlling the power consumption of the target controller (216). The power management circuit (220) receives the bus activity signal and generates the sequencing signal in response to the bus activity signal.

公开(公告)号：AU3297597A

公开(公告)日：1998-01-05

申请号：AU3297597

申请日：1997-05-27

Applicant: INTEL CORP

Inventor： REINHARDT DENNIS ,  KARDACH JAMES P ,  HORIGAN JOHN W ,  SONGER NEIL ,  GLEW ANDREW F

IPC: G06F9/48 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08 ,  G06F12/14 ,  G06F9/30 ,  G06F9/22 ,  G06F12/10

Abstract: A novel method and apparatus to cache System Management Mode (SMM) data with other data to improve performance and reduce latency of SMM handler routines. This method and apparatus allows SMM data and non-SMM data to be distinguished in the cache without requiring extra cache bits which can add to the cost of implementation. Since SMM data and non-SMM data can coexist in the cache, there is no need for time consuming cache flush cycles when switching between the two modes. Since SMM data can be cached, performance of SMM routines are improved. This method and apparatus defines the SMRAM address range to be a range of addresses representable by the tag, but not directly corresponding to installed main memory. When accesses are made to SMRAM addresses, they are redirected to an unused portion of main memory. Protection mechanisms may be implemented to limit access to these SMRAM addresses when not in SMM.

公开(公告)号：EP0902922A4

公开(公告)日：2000-06-21

申请号：EP97928811

申请日：1997-05-27

Applicant: INTEL CORP

Inventor： REINHARDT DENNIS ,  KARDACH JAMES P ,  HORIGAN JOHN W ,  SONGER NEIL ,  GLEW ANDREW F

IPC: G06F9/48 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08 ,  G06F12/14 ,  G06F9/30 ,  G06F9/22 ,  G06F12/10

CPC classification number: G06F12/1491 ,  G06F12/0284 ,  G06F12/0802 ,  G06F12/1441 ,  G06F12/1475

Abstract: A novel method and apparatus to cache System Management Mode (SMM) data with other data to improve performance and reduce latency of SMM handler routines. This method and apparatus allows SMM data and non-SMM data to be distinguished in the cache without requiring extra cache bits which can add to the cost of implementation. Since SMM data and non-SMM data can coexist in the cache, there is no need for time consuming cache flush cycles when switching between the two modes (1150). Since SMM data can be cached, performance of SMM routines are improved. This method and apparatus defines the SMRAM address range to be a range of addresses (1110) representable by the tag, but not directly corresponding to installed main memory. When accesses are made to SMRAM addresses, they are redirected to an unused portion of main memory. Protection mechanisms (1150) may be implemented to limit access to these SMRAM addresses when not in SMM.

公开(公告)号：EP0811197A4

公开(公告)日：1999-11-24

申请号：EP95911910

申请日：1995-02-24

Applicant: INTEL CORP

Inventor： DATTA SHAM ,  JOSHI JAYESH ,  KARDACH JAMES P

IPC: G06F1/32 ,  G06F13/42 ,  G06F13/00

CPC classification number: G06F1/3215 ,  G06F13/423

Abstract: A device and method for transferring data, address and status information concerning a former I/O bus cycle before a system management interrupt is initiated. A plurality of system management shadow registers (22) samples information from a system bus (16). Such information is obtained by a register accessing the plurality of system management shadow registers (22) through a common shadow port.

公开(公告)号：DE112013006266T5

公开(公告)日：2015-10-08

申请号：DE112013006266

申请日：2013-06-25

Applicant: INTEL CORP

Inventor： MACDONALD KIRSTY ,  KARDACH JAMES P ,  GIBSON PETER

IPC: G11B19/28

Abstract: Verschiedenartige Ausführungsformen sind im Allgemeinen auf das wiederkehrend periodische Durchlaufen des Antreibens von Plattenmedien eines Festplattenlaufwerks mit einem Motor gerichtet, um zu erlauben, dass sich die Drehung der Plattenmedien nur auf einen Schwellenwert der Drehzahl verlangsamt, um die Leistungserhaltung mit Verzögerungen beim Zugreifen auf Daten auszugleichen. Ein Verfahren umfasst das Antreiben von Plattenmedien eines Festplattenlaufwerks, um sich mit einer gewählten normalen Drehzahl zu drehen, das Abrufen von Daten, die auf den Plattenmedien gespeichert sind, wenn sich die Plattenmedien mit der normalen Drehzahl drehen, das Aufhören, die Plattenmedien anzutreiben, sich zu drehen, um den Plattenmedien zu erlauben, sich unter der Drehträgheit, die an die Plattenmedien weitergegeben wurde, zu drehen, das Überwachen einer Drehzahl der Plattenmedien und auf der Grundlage, dass die aktuelle Drehzahl auf einen unteren Schwellenwert der Drehzahl gefallen, der gewählt ist, kleiner als die normale Drehzahl zu sein, das Wiederaufnehmen des Antreibens der Plattenmedien, sich zu drehen. Andere Ausführungsformen werden beschrieben und beansprucht.