公开(公告)号：JP2013254524A

公开(公告)日：2013-12-19

申请号：JP2013195581

申请日：2013-09-20

Applicant: INTEL CORP

Inventor： CHINYA GAUTHAM N ,  HAUN WARNE ,  MATHAIKUTTY DEEPAK A ,  COLLINS JAMISON D ,  SCHUCHMAN ETHAN ,  HELD JAMES P ,  BHATT AJAY V ,  SETHI PRASHANT ,  WHALLEY STEPHEN F

IPC: G06F12/10 ,  G06F12/08

Abstract: PROBLEM TO BE SOLVED: To provide hardware support for virtual memory shared between local physical memory and remote physical memory.SOLUTION: A method comprises: receiving a memory access request including a virtual address; analyzing an entry corresponding to the virtual address stored in a translation lookaside buffer (TLB) of a processor in order to determine if a physical address (PA) corresponding to the virtual address is present in a local memory associated with the processor or a remote memory associated with an accelerator coupled to the processor via a non-coherent link; and if the PA is present in the remote memory, sending a reverse proxy execution request to the remote memory in order to perform the memory access request. The local memory and the remote memory collectively form a shared virtual memory space.

公开(公告)号：JP2011065650A

公开(公告)日：2011-03-31

申请号：JP2010205550

申请日：2010-09-14

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： CHINYA GAUTHAM N ,  WANG HONG ,  MATHAIKUTTY DEEPAK A ,  COLLINS JAMISON D ,  SCHUCHMAN ETHAN ,  HELD JAMES P ,  BHATT AJAY V ,  SETHI PRASHANT ,  WHALLEY STEPHEN F

IPC: G06F12/10 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08

CPC classification number: G06F12/1036 ,  G06F12/1027 ,  G06F12/121 ,  G06F2212/254

Abstract: PROBLEM TO BE SOLVED: To provide hardware support for a virtual memory shared between a local physical memory and a remote physical memory.
SOLUTION: A method includes the steps of: receiving a memory access request including a virtual address; analyzing an entry corresponding to the virtual address stored in a conversion look-aside buffer (TLB) of a processor, in order to determine whether a physical address (PA) corresponding to the virtual address exists in the remote memory attached to an accelerator connected to the processor, via the local memory or a non-coherent link attached to the processor; and transmitting a reverse proxy execution request to the remote memory, in order to execute the memory access request, when the PA exists in the remote memory. The local memory and the remote memory constitute a common virtual memory space.
COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为本地物理内存和远程物理内存之间共享的虚拟内存提供硬件支持。 解决方案：一种方法包括以下步骤：接收包括虚拟地址的存储器访问请求; 分析与存储在处理器的转换后备缓冲器（TLB）中的虚拟地址相对应的条目，以便确定与连接到加速器的加速器相连的远程存储器中是否存在与虚拟地址相对应的物理地址（PA） 处理器，经由本地存储器或连接到处理器的非相干链路; 并且当远程存储器中存在PA时，为了执行存储器访问请求，向远程存储器发送反向代理执行请求。 本地内存和远程内存构成了一个通用的虚拟内存空间。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：WO2010021844A3

公开(公告)日：2010-05-27

申请号：PCT/US2009052831

申请日：2009-08-05

Applicant: INTEL CORP ,  CHANDRA PRASHANT R ,  BHATT AJAY V ,  KAHN KEVIN ,  MCGOWAN STEVE

Inventor： CHANDRA PRASHANT R ,  BHATT AJAY V ,  KAHN KEVIN ,  MCGOWAN STEVE

IPC: H04L12/56

CPC classification number: G06F13/122 ,  H04L45/62 ,  H04L47/2491 ,  H04Q11/0062 ,  H04Q11/0066

Abstract: A device, method, and system are disclosed. In one embodiment the device includes a router to transmit data packets between multiple host controllers and one or more peripheral devices. The router can receive a data packet from a host controller and transmit the data packet to a peripheral device across a data transmission path. The peripheral device is coupled to the first data transmission path through a first universal multi-transport medium (UMTM) connector. The connector includes an optical coupling capable of transporting the first data packet within an optical signal and an electrical coupling capable of transporting the first data packet within an electrical signal.

Abstract translation: 公开了一种装置，方法和系统。 在一个实施例中，该设备包括用于在多个主机控制器和一个或多个外围设备之间传输数据分组的路由器。 路由器可以从主机控制器接收数据分组，并通过数据传输路径将数据分组传输到外围设备。 外围设备通过第一通用多传输介质（UMTM）连接器耦合到第一数据传输路径。 该连接器包括能够在光信号内传输第一数据包的光耦合和能够在电信号内传输第一数据包的电耦合。

公开(公告)号：AU703388B2

公开(公告)日：1999-03-25

申请号：AU3973095

申请日：1995-10-31

Applicant: INTEL CORP

Inventor： MORRISS JEFF CHARLES ,  KNOLL SHAUN ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M ,  BHATT AJAY V ,  CADAMBI SUDARSHAN BALA

IPC: G06F13/36 ,  G06F13/00 ,  G06F13/38 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64

Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.

公开(公告)号：AU4019995A

公开(公告)日：1996-05-23

申请号：AU4019995

申请日：1995-10-30

Applicant: INTEL CORP

Inventor： KNOLL SHAUN ,  MORRISS JEFF CHARLES ,  BHATT AJAY V ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M ,  CADAMBI SUDARSHAN BALA

IPC: G06F13/10 ,  G06F13/22 ,  G06F13/40 ,  H04L12/40 ,  H04L12/64 ,  G06F13/12

Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically generate and maintain a frame based polling schedule for polling the functions of the bus agents connected to the serial bus assembly and the serial bus elements themselves. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements support gathering of various critical operating characteristics by the bus controller. The circuitry and logic provided to the bus controller in turn generate the frame based polling schedule in accordance to these gathered critical operating characteristics, guaranteeing latencies and bandwidths to the isochronous functions of the isochronous peripherals. In certain embodiments, the circuitry and logic provided to the bus controller further adapts in real time its frame based polling schedule in like manner, responsive to live attachment/detachment of serial bus elements.

公开(公告)号：GB2308533B

公开(公告)日：1999-04-07

申请号：GB9707611

申请日：1995-10-31

Applicant: INTEL CORP

Inventor： MORRISS JEFF CHARLES ,  KNOLL SHAUN ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M ,  BHATT AJAY V ,  CADAMBI SUDARSHAN BALA

IPC: G06F13/00 ,  G06F13/36 ,  G06F13/38 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64

Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.

公开(公告)号：CA2202517A1

公开(公告)日：1996-05-09

申请号：CA2202517

申请日：1995-10-31

Applicant: INTEL CORP

Inventor： CADAMBI SUDARSHAN BALA ,  BHATT AJAY V ,  CALLAHAN SHELAGH ,  KNOLL SHAUN ,  MORRISS JEFF CHARLES

IPC: G06F12/06 ,  G06F13/38 ,  H04L12/40 ,  H04L12/64 ,  G06F13/20

Abstract: Circuitry and complementary logic are provided to a bus controller (14), a number of 1:n bus signal distributor (18), and a number of bus interfaces (22) of a hierarchical serial bus assembly for the bus controller to dynamically detect and manage the interconnection topology of the serial bus elements. The serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic support a hierarchical view of the serial bus elements (16), logically dividing the hierarchy into multiple tiers. This logical view of the serial bus elements is used by the bus controller to detect the presence of interconnected serial bus elements and the functions of the bus agents, i.e. the system unit and the interconnected peripheral, as well as assignment of addresses to the serial bus elements and the functions, at power on, reset, and during operation when serial bus elements are hot attached to or detached from the serial bus assembly.

公开(公告)号：BRPI1003466A2

公开(公告)日：2015-08-18

申请号：BRPI1003466

申请日：2010-09-16

Applicant: INTEL CORP

Inventor： CHINYA GAUTHAM N ,  WANG HONG ,  MATHAIKUTTY DEEPAK A ,  COLLINS JAMISON D ,  SCHUCHMAN ETHAN ,  HELD JAMES P ,  BHATT AJAY V ,  SETHI PRASHANT ,  WHALLEY STEPHEN F

IPC: G06F12/10

Abstract: Método, dispositivo e sistema de suporte de hardware para o compartilhamento de memória virtual entre memória física local e remota. Em uma realização, a presente invenção inclui uma unidade de gerenciamento de memória (mmu) que possui entradas para armazenar endereços virtuais para conversões de endereços físicos, em que cada entrada inclui um indicador de local para indicar se um local de memória para a entrada correspondente está presente em uma memória local ou remota. Dessa maneira, um espaço de memória virtual comum pode ser compartilhado entre as duas memórias, que podem ser separadas por um ou mais links não coerentes. Outras realizações são descritas e reivindicadas

公开(公告)号：DE102010035603A1

公开(公告)日：2011-04-07

申请号：DE102010035603

申请日：2010-08-27

Applicant: INTEL CORP

Inventor： CHINYA GAUTHAM N ,  SCHUCHMAN ETHAN ,  WANG HONG ,  HELD JAMES P ,  MATHAIKUTTY DEEPAK A ,  BHATT AJAY V ,  COLLINS JAMISON D ,  SETHI PRASHANT ,  WHALLEY STEPHEN F

IPC: G06F12/10 ,  G06F9/30 ,  G06F12/08 ,  G06F13/00

公开(公告)号：DE19581234B4

公开(公告)日：2008-03-20

申请号：DE19581234

申请日：1995-10-31

Applicant: INTEL CORP

Inventor： MORRISS JEFF CHARLES ,  KNOLL SHAUN ,  NIZAR PUTHIYA KOTTAL ,  HASLAM RICHARD M ,  BHATT AJAY V ,  CADAMBI SUDARSHAN BALA

IPC: G06F13/36 ,  G06F13/37 ,  G06F13/00 ,  G06F13/38 ,  G06F13/42 ,  H04L12/40 ,  H04L12/64

Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical bus assembly for conducting data communication transactions between bus agents interconnected to the hierarchical bus assembly. The hierarchical serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic of the serial bus elements implement a number of elemental packets and a number of transaction protocols, employing a master/slave model of transaction flow control. Data communication transactions are conducted using the elemental packets and in accordance to the transaction protocols. In some embodiments, these circuitry and complementary logic of the serial bus elements are also used to conduct connection management transactions between the serial bus elements. The connection management transactions are conducted in like manner as the data communication transactions.