公开(公告)号：AU8377098A

公开(公告)日：1999-04-12

申请号：AU8377098

申请日：1998-06-26

Applicant: INTEL CORP

Inventor： GAFKEN ANDREW H ,  BENNETT JOSEPH A ,  POISNER DAVID I

IPC: G06F13/28 ,  G06F3/00

Abstract: A system including a host coupled to a memory device and a peripheral controller device. The host is coupled to the peripheral controller device via a bus having a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The peripheral controller device performs direct memory access (DMA) transactions with the memory device via the host and the bus.

公开(公告)号：SG146429A1

公开(公告)日：2008-10-30

申请号：SG2004029500

申请日：2004-05-21

Applicant: INTEL CORP

Inventor： POISNER DAVID I

IPC: G06F3/00 ,  G06F3/06 ,  G06F21/00 ,  G06F1/00 ,  G06F12/00

Abstract: TRUSTED INPUT FOR MOBILE PLATFORM TRANSACTIONS According to one embodiment, computer system is disclosed. The computer system includes a central processing unit (CPU), and a chipset coupled to the CPU including protected registers. The computer system also includes a micro-controller coupled to the chipset to perform scans to receive key-matrix data, wherein trusted software accesses the key-matrix data via the protected registers to ensure the authenticity of the data.

公开(公告)号：GB2345170B

公开(公告)日：2002-12-18

申请号：GB0007301

申请日：1998-07-07

Applicant: INTEL CORP

Inventor： GAFKEN ANDREW H ,  BENNETT JOSEPH A ,  POISNER DAVID I

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/10 ,  G06F13/42 ,  G06F9/445

Abstract: A system having a bus coupled to a host and a memory device. The bus may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device may store system start-up information and communicate this information with the host over the bus.

公开(公告)号：GB2345170A

公开(公告)日：2000-06-28

申请号：GB0007301

申请日：1998-07-07

Applicant: INTEL CORP

Inventor： GAFKEN ANDREW H ,  BENNETT JOSEPH A ,  POISNER DAVID I

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/10 ,  G06F13/42 ,  G06F9/445

Abstract: A system having a bus (124) coupled to a host (102) and a memory device (108). The bus (124) may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device (108) may store system start-up information and communicate this information with the host (102) over the bus (124).

公开(公告)号：MY146723A

公开(公告)日：2012-09-14

申请号：MYPI20032123

申请日：2003-06-06

Applicant: INTEL CORP

Inventor： SUTTON JAMES A II ,  GEORGE ROBERT T ,  BURGESS BRADLEY G ,  GRAWROCK DAVID W ,  UHLIG RICHARD A ,  POISNER DAVID I ,  GLEW ANDREW F ,  HALL CLIFFORD D ,  SMITH LAWRENCE O III ,  GILBERT NEIGER ,  KOZUCH MICHAEL A

IPC: G06F9/46 ,  G06F1/00 ,  G06F12/14 ,  G06F9/48 ,  G06F21/00

Abstract: A SYSTEM AND METHOD FOR PERMITTING THE EXECUTION OF SYSTEM MANAGEMENT MODE (SMM) CODE DURING SECURE OPERATIONS IN A MICROPROCESSOR SYSTEM IS DESCRIBED. IN ONE EMBODIMENT, THE SYSTEM MANAGEMENT INTERRUPT (SMI) MAY BE FIRST DIRECTED TO A HANDLER IN A SECURED VIRTUAL MACHINE MONITOR (SVMM). THE SMI MAY THEN BE REDIRECTED TO SMM CODE LOCATED IN A VIRTUAL MACHINE (VM) THAT IS UNDER THE SECURITY CONTROL OF THE SVMM. THIS REDIRECTION MAY BE ACCOMPLISHED BY ALLOWING THE SVMM TO READ AND WRITE THE SYSTEM MANAGEMENT (SM) BASE REGISTER IN THE PROCESSOR.

公开(公告)号：HK1028459A1

公开(公告)日：2001-02-16

申请号：HK00107601

申请日：2000-11-27

Applicant: INTEL CORP

Inventor： GAFKEN ANDREW H ,  BENNETT JOSEPH A ,  POISNER DAVID I

IPC: G06F13/28 ,  G06F

Abstract: A system including a host coupled to a memory device and a peripheral controller device. The host is coupled to the peripheral controller device via a bus having a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The peripheral controller device performs direct memory access (DMA) transactions with the memory device via the host and the bus.

公开(公告)号：HK1026489A1

公开(公告)日：2000-12-15

申请号：HK00105694

申请日：2000-09-09

Applicant: INTEL CORP

Inventor： GAFKEN ANDREW H ,  BENNETT JOSEPH A ,  POISNER DAVID I

IPC: G06F12/00 ,  G06F13/10 ,  G06F13/16 ,  G06F13/42 ,  G06F

Abstract: A system having a bus coupled to a host and a memory device. The bus may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device may store system start-up information and communicate this information with the host over the bus.

公开(公告)号：DE19882696T1

公开(公告)日：2000-10-26

申请号：DE19882696

申请日：1998-07-07

Applicant: INTEL CORP

Inventor： GAFKEN ANDREW H ,  BENNETT JOSEPH A ,  POISNER DAVID I

IPC: G06F12/00 ,  G06F13/10 ,  G06F13/16 ,  G06F13/42 ,  G06F13/00

Abstract: A system having a bus coupled to a host and a memory device. The bus may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device may store system start-up information and communicate this information with the host over the bus.

公开(公告)号：AU8475798A

公开(公告)日：1999-04-12

申请号：AU8475798

申请日：1998-07-07

Applicant: INTEL CORP

Inventor： GAFKEN ANDREW H ,  BENNETT JOSEPH A ,  POISNER DAVID I

IPC: G06F13/10 ,  G06F12/00 ,  G06F13/16 ,  G06F13/42 ,  G06F13/00

Abstract: A system having a bus coupled to a host and a memory device. The bus may include a plurality of general purpose signal lines to carry time-multiplexed address, data, and control information. The memory device may store system start-up information and communicate this information with the host over the bus.

公开(公告)号：EP2727331A4

公开(公告)日：2015-06-17

申请号：EP12807708

申请日：2012-06-30

Applicant: INTEL CORP

Inventor： KRIMON YURI I ,  POISNER DAVID I

IPC: H04N5/225 ,  G06F3/01 ,  G06F3/048 ,  G06F17/21 ,  G06K9/00 ,  G06K9/20 ,  G06K9/36 ,  G06T7/00 ,  G09G5/22 ,  G09G5/26 ,  H04N1/393

CPC classification number: G09G5/22 ,  G06F3/012 ,  G06F3/04847 ,  G06F17/214 ,  G06K9/00221 ,  G09G5/26 ,  G09G2320/08 ,  G09G2354/00