公开(公告)号：JP2006185453A

公开(公告)日：2006-07-13

申请号：JP2006009928

申请日：2006-01-18

Applicant: INTEL CORP

Inventor： LIN DERRICK ,  VAKKALAGADDA ROMAMOHAN R ,  GLEW ANDREW F ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI HIDEKAZU ,  EITAN BENNY

IPC: G06F7/00 ,  G06F9/305 ,  G06F9/30 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

Abstract: PROBLEM TO BE SOLVED: To incorporate a set of instructions for processing packed data in a processor so as to have compatibility with existing software and hardware. SOLUTION: Both of a set of packed data instructions are performed before performance of floating point instruction to contents of a single logic register file which is at least partially aliased and to which a plurality of tags correspond, at a point of time between staring of performance of a first instruction of the packed data instruction set and completion of performance of a first instruction of a floating point instruction set, the plurality of tags corresponding to the aliased register in at least a single logic register file are changed to a not empty state and the tag identifies whether or not the register in the single logic register file is empty. COPYRIGHT: (C)2006,JPO&NCIPI

公开(公告)号：JP2004152318A

公开(公告)日：2004-05-27

申请号：JP2003417823

申请日：2003-12-16

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： LIN DERRICK ,  VAKKALAGADDA ROMAMOHAN R ,  GLEW ANDREW F ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI HIDEKAZU ,  EITAN BENNY

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/30123 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30134 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: PROBLEM TO BE SOLVED: To install a set of instructions in a processor for processing pack data for furnishing compatibility with existing software and hardware. SOLUTION: For executing both of a set of pack data instructions and a set of floating point instructions on contents, which are aliased partially at least and correspond to a plurality of tags, of a single logical register file, the set of pack data instructions are executed before execution of the set of floating point instructions. At a certain time between a start of execution of a first instruction in the set of pack data instructions and execution of a first instruction in the set of floating point instructions, a plurality of tags matching an alias register in at least a single logical register file are changed into a non-empty condition, and the tags determine whether the register in a signal logical register file is empty or not. COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2011081790A

公开(公告)日：2011-04-21

申请号：JP2010213238

申请日：2010-09-24

Applicant: Intel Corp ,  インテル コーポレイション

Inventor： PATEL BAIJU V ,  GOPALAKRISHNA RAJEEV ,  GLEW ANDREW F ,  KUSHLIS ROBERT J ,  VAN DYKE DON ALAN ,  CIHULA JOSEPH FRANK ,  MALLICK ASIT K ,  CROSSLAND JAMES B ,  NEIGER GILBERT ,  RODGERS SCOTT DION ,  DIXON MARTIN GUY ,  CHARNEY MARK JAY ,  GOTTLIEB JOCOB

IPC: G06F9/34

CPC classification number: G06F9/3013 ,  G06F9/30105 ,  G06F9/30112 ,  G06F9/32 ,  G06F9/342 ,  G06F9/35 ,  G06F12/1441

Abstract: PROBLEM TO BE SOLVED: To allow lower and upper bounds of an object pointed to by a pointer to be automatically checked during execution of a program in programming languages such as C and C++ programs. SOLUTION: A processor 200 has default registers 202 and bound registers 204 which represent hardware register extensions of the default registers. The bound registers 204 maintain the association of metadata with its corresponding data. By providing the association between the default registers 202 and the bound registers 204, the calling convention of these registers 202 remains the same. The metadata being held at the bound registers 204 may be used to specify a range of memory addresses which can be accessed (loaded/stored) using the processor 200. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：允许在编程语言（如C和C ++程序）中执行程序期间自动检查由指针指向的对象的下限和上限。 解决方案：处理器200具有表示默认寄存器的硬件寄存器扩展的默认寄存器202和绑定寄存器204。 绑定寄存器204保持元数据与其相应数据的关联。 通过提供默认寄存器202和绑定寄存器204之间的关联，这些寄存器202的调用约定保持不变。 保留在绑定寄存器204的元数据可以用于指定可以使用处理器200访问（加载/存储）的存储器地址的范围。版权所有：（C）2011，JPO＆INPIT

公开(公告)号：JP2004152319A

公开(公告)日：2004-05-27

申请号：JP2003417826

申请日：2003-12-16

Applicant: Intel Corp ,  インテル・コーポレーション

Inventor： LIN DERRICK ,  VAKKALAGADDA ROMAMOHAN R ,  GLEW ANDREW F ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI HIDEKAZU ,  EITAN BENNY

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/30123 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30134 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: PROBLEM TO BE SOLVED: To use a single physical register file under an alias to execute a floating point instruction and a pack data instruction. SOLUTION: A first instruction is received, it is determined whether the first instruction is the floating point instruction or a second type instruction, and it is determined whether a processor including first and second pairs of physical registers is in a floating point mode or in a second type mode. If the processor is in the second type mode when the first instruction is the floating point instruction, transition to the floating point mode is carried out, and the floating point instruction is operated by using the first pair of physical registers. If the processor is not in the floating point mode, transition to the second type mode is carried out, and the second type instruction is operated by using the second pair of physical registers partially under an alias to the first pair of physical registers so that the first pair of physical registers and the second pair of physical registers appear to be a single logical register file logically. COPYRIGHT: (C)2004,JPO

公开(公告)号：WO2010117528A3

公开(公告)日：2011-01-27

申请号：PCT/US2010026558

申请日：2010-03-08

Applicant: INTEL CORP ,  HARRIMAN DAVID J ,  GLEW ANDREW F

Inventor： HARRIMAN DAVID J ,  GLEW ANDREW F

IPC: G06F13/14 ,  G06F9/46 ,  G06F12/02 ,  G06F15/16

CPC classification number: G06F13/16 ,  G06F9/46 ,  G06F12/02 ,  G06F12/063 ,  G06F12/1027 ,  G06F13/14 ,  G06F15/16 ,  G06F2212/654

Abstract: Methods and apparatus for opportunistic improvement of Memory Mapped Input/Output (MMIO) request handling (e.g., based on target reporting of space requirements) are described. In one embodiment, logic in a processor may detect one or more bits in a message that is to be transmitted from an input/output (I/O) device. The one or more bits may indicate memory mapped I/O (MMIO) information corresponding to one or more attributes of the I/O device. Other embodiments are also disclosed.

Abstract translation: 描述了存储映射输入/输出（MMIO）请求处理的机会性改进的方法和装置（例如，基于空间要求的目标报告）。 在一个实施例中，处理器中的逻辑可以检测要从输入/输出（I / O）设备发送的消息中的一个或多个位。 一个或多个比特可以指示对应于I / O设备的一个或多个属性的存储器映射I / O（MMIO）信息。 还公开了其他实施例。

公开(公告)号：EP0783735A4

公开(公告)日：2004-10-20

申请号：EP95931580

申请日：1995-08-24

Applicant: INTEL CORP

Inventor： GLEW ANDREW F ,  HINTON GLENN J

IPC: G06F9/312 ,  G06F9/38 ,  G06F12/08

CPC classification number: G06F9/30043 ,  G06F9/3824 ,  G06F9/3842 ,  G06F9/3857 ,  G06F12/0804 ,  G06F12/0888

Abstract: A memory-type value identifying the type of memory contained with a range of memory locations is explicitly stored within a microprocessor (200-216). Prior to processing a memory micro-instruction such as a load or store, the memory-type is determined (214-216) for the memory location identified by the memory micro-instruction. Once the memory-type is known the memory micro-instruction is processed (218-230) in accordance with any one of a number or processing protocols including write-through processing (220), write-back processing (222), write-protect processing (224), restricted-cacheability processing (226), uncacheable speculatable write-combining processing (230), or uncacheable processing (228). By providing memory-type information explicitly within the microprocessor the protocol by which the micro-instruction is processed may be efficiently tailored to the memory-type. In an exemplary embodiment, the microprocessor is an out-of-order microprocessor (200) capable of generating speculative memory microinstructions (202-204).

公开(公告)号：EP0902922A4

公开(公告)日：2000-06-21

申请号：EP97928811

申请日：1997-05-27

Applicant: INTEL CORP

Inventor： REINHARDT DENNIS ,  KARDACH JAMES P ,  HORIGAN JOHN W ,  SONGER NEIL ,  GLEW ANDREW F

IPC: G06F9/48 ,  G06F12/02 ,  G06F12/06 ,  G06F12/08 ,  G06F12/14 ,  G06F9/30 ,  G06F9/22 ,  G06F12/10

CPC classification number: G06F12/1491 ,  G06F12/0284 ,  G06F12/0802 ,  G06F12/1441 ,  G06F12/1475

Abstract: A novel method and apparatus to cache System Management Mode (SMM) data with other data to improve performance and reduce latency of SMM handler routines. This method and apparatus allows SMM data and non-SMM data to be distinguished in the cache without requiring extra cache bits which can add to the cost of implementation. Since SMM data and non-SMM data can coexist in the cache, there is no need for time consuming cache flush cycles when switching between the two modes (1150). Since SMM data can be cached, performance of SMM routines are improved. This method and apparatus defines the SMRAM address range to be a range of addresses (1110) representable by the tag, but not directly corresponding to installed main memory. When accesses are made to SMRAM addresses, they are redirected to an unused portion of main memory. Protection mechanisms (1150) may be implemented to limit access to these SMRAM addresses when not in SMM.

公开(公告)号：EP0868689A4

公开(公告)日：2000-02-16

申请号：EP96944983

申请日：1996-12-17

Applicant: INTEL CORP

Inventor： LIN DERRICK ,  VAKKALAGADDA RAMAMOHAN R ,  GLEW ANDREW F ,  MENNEMEIER LARRY M ,  PELEG ALEXANDER D ,  BISTRY DAVID ,  MITTAL MILLIND ,  DULONG CAROLE ,  KOWASHI EIICHI ,  EITAN BENNY

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48

CPC classification number: G06F9/30123 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30134 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: A method and apparatus for executing floating point and packed data instructions using a single physical register file that is aliased. According to one aspect of the invention, processor is provided that includes a decode unit (1002), a mapping unit (1004), and a storage unit (1006). The decode unit (1002) is configured to decode instructions and their operands from at least one instruction set including at least a first and second set of instructions. The storage unit (1006) includes a physical register file (1020). The mapping unit (1004) is configured to map operands used by the first set of instructions to the physical register file in a stock referenced manner. In addition, the mapping unit (1004) is configured to map operands used by the second set of instructions to the same physical register file in a non-stack reference manner.

Abstract translation: 一种用于执行浮点和紧缩数据说明，用一个单一的物理寄存器文件的方法和装置也被混叠。 。根据本发明的一个方面，提供了一种处理器做包括一解码单元，映射单元，以及存储单元。 解码单元被配置为指令和其操作数从至少一个指令集包括至少一个第一和第二组指令进行解码。 所述存储单元包括一个物理寄存器文件。 所述映射单元被配置为在一个股票引用方式使用由第一组的说明将物理寄存器文件的操作数。 另外，映射单元被配置成映射在一个非堆叠参考方式使用由所述第二组指令到相同的物理寄存器堆的操作数。

公开(公告)号：GB2291513B

公开(公告)日：1999-04-28

申请号：GB9414028

申请日：1994-07-12

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  GLEW ANDREW F ,  NATARAJAN SUBRAMANIAN

IPC: G06F9/38

公开(公告)号：SE9503951D0

公开(公告)日：1995-11-08

申请号：SE9503951

申请日：1995-11-08

Applicant: INTEL CORP

Inventor： HOYT BRADLEY D ,  HINTON GLENN J ,  GLEW ANDREW F ,  NATARAJAN SUBRAMANIAN

IPC: G06F9/38 ,  G06F

Abstract: The branch prediction appts maintains both speculative history (25) and actual history (22) for each branch instruction in a branch target buffer. The actual branch history contains the branch history for fully resolved occurrences of the branch instruction. The speculative branch history contains the actual history and in addition the history of recent branch predictions. If the speculative branch history contains any recent predictions, then a speculation bit (24) is set. When the speculative bit is set, this indicates that there is a speculative history for a branch. Therefore, when the speculation bit is set the speculative history is used to make branch predictions. If a mis-prediction is made for the branch, the speculative bit is cleared since the speculative history contains inaccurate branch history.