公开(公告)号：US20200319806A1

公开(公告)日：2020-10-08

申请号：US16715747

申请日：2019-12-16

Applicant: Intel Corporation

Inventor： Inder M. Sodhi ,  Alon Naveh ,  Doron Rajwan ,  Ryan D. Wells ,  Eric C. Samson

IPC: G06F3/06 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/3287

Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.

公开(公告)号：US10372197B2

公开(公告)日：2019-08-06

申请号：US15367330

申请日：2016-12-02

Applicant: Intel Corporation

Inventor： Krishnakanth V. Sistla ,  Jeremy Shrall ,  Stephen H. Gunther ,  Efraim Rotem ,  Alon Naveh ,  Eliezer Weissmann ,  Anil Aggarwal ,  Martin T. Rowland ,  Ankush Varma ,  Ian M. Steiner ,  Matthew Bace ,  Avinash N. Ananthakrishnan ,  Jason Brandt

IPC: G06F1/26 ,  G06F1/3234 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/32

Abstract: In one embodiment, the present invention includes a processor having a core and a power controller to control power management features of the processor. The power controller can receive an energy performance bias (EPB) value from the core and access a power-performance tuning table based on the value. Using information from the table, at least one setting of a power management feature can be updated. Other embodiments are described and claimed.

公开(公告)号：US20190155606A1

公开(公告)日：2019-05-23

申请号：US16259880

申请日：2019-01-28

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Boris Ginzburg ,  Alon Naveh ,  Nadav Shulman ,  Ronny Ronen

IPC: G06F9/30 ,  G06F9/455 ,  G06F9/38 ,  G06F11/34 ,  G06F1/3234

Abstract: Disclosed embodiments relate to processing logic for performing function operations. In one example, and apparatus includes an execution unit within a processor to execute a code block, power management hardware coupled to the execution unit, wherein the power management hardware is to monitor a first execution of the code block, store a micro-architectural context of the processor in a metadata block associated with the code block, the micro-architectural context including performance data resulting from the first execution of the code block, the performance data comprising power and energy usage data, and power management related parameters, read the associated metadata block upon a second execution of the code block, and tune the second execution based on the performance data stored in the associated metadata block to increase efficiency of executing the code block.

公开(公告)号：US20180260153A1

公开(公告)日：2018-09-13

申请号：US15786424

申请日：2017-10-17

Applicant: Intel Corporation

Inventor： Inder M. Sodhi ,  Alon Naveh ,  Doron Rajwan ,  Ryan D. Wells ,  Eric C. Samson

IPC: G06F3/06 ,  G06F1/32

CPC classification number: G06F3/0625 ,  G06F1/3206 ,  G06F1/3278 ,  G06F1/3287 ,  G06F3/0634 ,  G06F3/0673 ,  Y02D10/157 ,  Y02D10/171

Abstract: Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.

公开(公告)号：US10013047B2

公开(公告)日：2018-07-03

申请号：US15143309

申请日：2016-04-29

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Oren Lamdan ,  Alon Naveh

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/20 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/0875 ,  G06F9/30

CPC classification number: G06F1/3287 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3275 ,  G06F1/3296 ,  G06F9/30083 ,  G06F9/3814 ,  G06F12/0862 ,  G06F12/0875 ,  G06F2212/452 ,  G06F2212/602 ,  Y02D10/126 ,  Y02D10/16 ,  Y02D10/172 ,  Y02D50/20

Abstract: For one disclosed embodiment, a processor comprises a plurality of processor cores to operate at variable performance levels. One of the plurality of processor cores may operate at one time at a performance level different than a performance level at which another one of the plurality of processor cores may operate at the one time. The plurality of processor cores are in a same package. Logic of the processor is to set one or more operating parameters for one or more of the plurality of processor cores. Logic of the processor is to monitor activity of one or more of the plurality of processor cores. Logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity. The logic to constrain power is to limit a frequency at which one or more of the plurality of processor cores may be set. Other embodiments are also disclosed.

公开(公告)号：US20170269672A9

公开(公告)日：2017-09-21

申请号：US14966708

申请日：2015-12-11

Applicant: Intel Corporation

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  John B. Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/1441 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/314 ,  G11C7/1072 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/32 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20 ,  Y02P80/11 ,  Y10T307/305 ,  Y10T307/406 ,  Y10T307/582 ,  Y10T307/826

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

公开(公告)号：US09766683B2

公开(公告)日：2017-09-19

申请号：US15270206

申请日：2016-09-20

Applicant: Intel Corporation

Inventor： Shaun M. Conrad ,  William Knolla ,  Douglas R. Moran ,  Sm M. Rahman ,  Jawad Haj-Yihia ,  Alon Naveh ,  Ohad Falik

IPC: G06F13/40 ,  G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F13/40 ,  G06F13/4027 ,  G06F13/4068 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D10/172

Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.

公开(公告)号：US09477627B2

公开(公告)日：2016-10-25

申请号：US13727052

申请日：2012-12-26

Applicant: Intel Corporation

Inventor： Shaun M. Conrad ,  William Knolla ,  Douglas R. Moran ,  SM M. Rahman ,  Jawad Haj-Yihia ,  Alon Naveh ,  Ohad Falik

IPC: G06F13/40 ,  G06F1/32

CPC classification number: G06F1/3206 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3296 ,  G06F13/40 ,  G06F13/4027 ,  G06F13/4068 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/151 ,  Y02D10/172

Abstract: A processor includes at least one core, a power control unit, and a first interconnect to couple with a peripheral controller. The first interconnect is to provide a first uni-directional communication path for communication of first power management data from the processor to the peripheral controller. Other embodiments are described and claimed.

Abstract translation: 处理器包括至少一个核心，功率控制单元和与外围控制器耦合的第一互连。 第一互连是提供用于从处理器到外围控制器的第一电力管理数据的通信的第一单向通信路径。 描述和要求保护其他实施例。

公开(公告)号：US20160091958A1

公开(公告)日：2016-03-31

申请号：US14959549

申请日：2015-12-04

Applicant: Intel Corporation

Inventor： Sanjeev Jahagirdar ,  Varghese George ,  John Conrad ,  Robert Milstrey ,  Stephen A. Fischer ,  Alon Naveh ,  Shai Rotem

IPC: G06F1/32

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3246 ,  G06F1/3275 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/4418 ,  G06F11/1441 ,  G06F12/084 ,  G06F12/0875 ,  G06F2212/281 ,  G06F2212/305 ,  G06F2212/314 ,  G11C7/1072 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/32 ,  Y02D10/152 ,  Y02D10/172 ,  Y02D50/20 ,  Y02P80/11 ,  Y10T307/305 ,  Y10T307/406 ,  Y10T307/582 ,  Y10T307/826

Abstract: Embodiments of the invention relate to a method and apparatus for a zero voltage processor sleep state. A processor may include a dedicated cache memory. A voltage regulator may be coupled to the processor to provide an operating voltage to the processor. During a transition to a zero voltage power management state for the processor, the operational voltage applied to the processor by the voltage regulator may be reduced to approximately zero and the state variables associated with the processor may be saved to the dedicated cache memory.

公开(公告)号：US09268378B2

公开(公告)日：2016-02-23

申请号：US13931128

申请日：2013-06-28

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Alon Naveh ,  Doron Rajwan ,  Nadav Shulman ,  Eliezer Weissmann

IPC: G06F1/20 ,  G06F1/32

CPC classification number: G06F1/206 ,  G06F1/203 ,  G06F1/3206 ,  G06F1/3215 ,  G06F1/3243 ,  G06F1/3287 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D50/20

Abstract: In one embodiment an apparatus includes a temperature sensor to perform a multiplicity of junction temperature measurements for a component in a platform, a controller comprising logic at least a portion of which is in hardware. The logic may receive from the temperature sensor the multiplicity of junction temperature measurements and may instruct the component to perform a first power down action of the component when a junction temperature measurement exceeds a first threshold, and may instruct the component to perform a second power down action of the component when an average junction temperature based on the multiplicity of junction temperature measurements exceeds a second threshold. Other embodiments are disclosed and claimed.

Abstract translation: 在一个实施例中，一种装置包括温度传感器，用于对平台中的部件执行多个结温测量，控制器包括至少其一部分处于硬件中的逻辑。 逻辑可以从温度传感器接收多个结温度测量值，并且当结温度测量超过第一阈值时可以指示组件执行部件的第一次掉电动作，并且可以指示组件执行第二次掉电 当基于结温度测量的多重性的平均结温超过第二阈值时，组分的作用。 公开和要求保护其他实施例。