公开(公告)号：US20240320161A1

公开(公告)日：2024-09-26

申请号：US18575832

申请日：2021-08-20

Applicant: Intel Corporation

Inventor： Kaijie Guo ,  Qianjun Xie ,  Weigang Li ,  Junyuan Wang ,  Ashok Raj ,  Zijuan Fan

IPC: G06F12/1045 ,  G06F9/30

CPC classification number: G06F12/1045 ,  G06F9/3016 ,  G06F2212/50

Abstract: Systems, methods, and apparatuses to support a device translation lookaside buffer pre-translation instruction are described. A hardware system includes an input/output device, an input/output memory controller to perform a direct memory access of a memory for the input/output device, and a processor core separate from the input/output device and comprising a decoder circuit to decode a single instruction into a decoded single instruction, the single instruction including one or more fields to identify a virtual address to physical address mapping for the input/output device in the memory, and an opcode to indicate an execution circuit is to store the virtual address to physical address mapping into a translation lookaside buffer within the input/output device, and the execution circuit to execute the decoded single instruction according to the opcode.

公开(公告)号：US11929927B2

公开(公告)日：2024-03-12

申请号：US17129756

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Pratik M. Marolia ,  Rajesh M. Sankaran ,  Ashok Raj ,  Nrupal Jani ,  Parthasarathy Sarangam ,  Robert O. Sharp

IPC: G06F13/28 ,  G06F12/1081 ,  H04L45/60 ,  H04L45/74 ,  H04L49/90

CPC classification number: H04L45/742 ,  G06F12/1081 ,  G06F13/28 ,  H04L45/60 ,  H04L49/9068

Abstract: A network interface controller can be programmed to direct write received data to a memory buffer via either a host-to-device fabric or an accelerator fabric. For packets received that are to be written to a memory buffer associated with an accelerator device, the network interface controller can determine an address translation of a destination memory address of the received packet and determine whether to use a secondary head. If a translated address is available and a secondary head is to be used, a direct memory access (DMA) engine is used to copy a portion of the received packet via the accelerator fabric to a destination memory buffer associated with the address translation. Accordingly, copying a portion of the received packet through the host-to-device fabric and to a destination memory can be avoided and utilization of the host-to-device fabric can be reduced for accelerator bound traffic.

公开(公告)号：US11307996B2

公开(公告)日：2022-04-19

申请号：US16206516

申请日：2018-11-30

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Ashok Raj ,  Wei P. Chen ,  Theodros Yigzaw ,  John Holm

IPC: G06F12/1027 ,  G06F12/0864 ,  G06F13/16 ,  G06F11/22 ,  G06F9/38

Abstract: In an embodiment, a processor for reverse translation includes a plurality of processing engines (PEs) to execute threads and a reverse translation circuit. The reverse translation circuit is to: determine a target module address of a corrupt portion of a memory module; determine a plurality of system physical address (SPA) addresses associated with the memory module; and for each SPA address in the plurality of SPA addresses, translate the SPA address into a translated module address, and in response to a determination that the translated module address matches the target module address, log the SPA address as a result of a reverse translation of the target module address. Other embodiments are described and claimed.

公开(公告)号：US11269782B2

公开(公告)日：2022-03-08

申请号：US16772765

申请日：2018-03-28

Applicant: INTEL CORPORATION

Inventor： Kun Tian ,  Xiao Zheng ,  Ashok Raj ,  Sanjay Kumar ,  Rajesh Sankaran

IPC: G06F12/1036 ,  G06F9/455 ,  G06F12/1081

Abstract: Embodiment of this disclosure provides a mechanism to extend a workload instruction to include both untranslated and translated address space identifiers (ASIDs). In one embodiment, a processing device comprising a translation manager is provided. The translation manager receives a workload instruction from a guest application. The workload instruction comprises an untranslated (ASID) and a workload for an input/output (I/O) device. The untranslated ASID is translated to a translated ASID. The translated ASID inserted into a payload of the workload instruction. Thereupon, the payload is provided to a work queue of the I/O device to execute the workload based in part on at least one of: the translated ASID or the untranslated ASID.

公开(公告)号：US10324852B2

公开(公告)日：2019-06-18

申请号：US15374796

申请日：2016-12-09

Applicant: INTEL CORPORATION

Inventor： Theodros Yigzaw ,  Ashok Raj ,  Robert C. Swanson ,  Mohan J. Kumar

IPC: G06F11/00 ,  G06F12/0868 ,  G06F11/20 ,  G06F12/109

Abstract: One embodiment provides for a data processing system comprising a multi-level system memory including a first memory level of volatile memory and a second memory level that is larger and slower in comparison with the first memory level. The second memory level includes non-volatile memory and can additionally include volatile memory. The multi-level system memory includes a multi-level memory controller including logic to manage a list of faulty addresses within the multi-level system memory. The multi-level memory controller can manage a list of faulty addresses. The multi-level memory controller is configured to satisfy a request for data stored in the first memory level from the second memory level when the data is stored in an address on the list of faulty addresses.

公开(公告)号：US10318368B2

公开(公告)日：2019-06-11

申请号：US15168999

申请日：2016-05-31

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Theodros Yigzaw

IPC: G06F11/00 ,  G06F11/07

Abstract: In accordance with implementations disclosed herein, there is provided systems and methods for enabling error status and reporting in a machine check environment. A processing device includes an error status register and an error status component communicably coupled to the error status register. The error status component determines that a machine check error (MCE) is a first correctable error (CE) and sets a first error status corresponding to the first CE in the error status register based on a threshold value. The threshold value is based on a type of the first CE.

公开(公告)号：US10157142B2

公开(公告)日：2018-12-18

申请号：US15280965

申请日：2016-09-29

Applicant: INTEL CORPORATION

Inventor： Ashok Raj ,  Sivakumar Radhakrishnan ,  Dan J. Williams ,  Vishal Verma ,  Narayan Ranganathan ,  Chet R. Douglas

IPC: G06F12/00 ,  G06F12/10 ,  G06F3/06

Abstract: In one embodiment, a block data transfer interface employing offload data transfer engine in accordance with the present description includes an offload data transfer engine executing a data transfer command set to transfer a block of data in a transfer data path from a source memory to a new region of a destination memory, wherein the transfer data path bypasses a central processing unit to minimize or reduce involvement of the central processing unit in the block transfer. In response to a successful transfer indication, a logical address is re-mapped to a physical address of the new region of the destination memory, instead of a physical address of the original region of the destination memory. In one embodiment, the re-mapping is performed by a central processing unit. In another embodiment, the re-mapping is performed by the offload data transfer engine. Other aspects are described herein.

公开(公告)号：US20180188966A1

公开(公告)日：2018-07-05

申请号：US15393935

申请日：2016-12-29

Applicant: Intel Corporation

Inventor： Sarathy Jayakumar ,  Mohan J. Kumar ,  Ashok Raj ,  Hemalatha Gurumoorthy ,  Ronald N. Story

IPC: G06F3/06

CPC classification number: G06F3/065 ,  G06F3/0619 ,  G06F3/0673 ,  G06F11/1666 ,  G06F11/2056 ,  G06F11/2094

Abstract: A systems and methods for dynamic address based minoring are disclosed. A system may include a processor, comprising a mirror address range register to store data indicating a location and a size of a first portion of a system memory to be mirrored. The processor may further include a memory controller coupled to the mirror address range register and including circuitry to cause a second portion of the system memory to mirror the first portion of the system memory.

公开(公告)号：US20180165207A1

公开(公告)日：2018-06-14

申请号：US15374796

申请日：2016-12-09

Applicant: INTEL CORPORATION

Inventor： Theodros Yigzaw ,  Ashok Raj ,  Robert C. Swanson ,  Mohan J. Kumar

IPC: G06F12/0868 ,  G06F11/20 ,  G06F12/109

CPC classification number: G06F12/0868 ,  G06F11/2094 ,  G06F12/0804 ,  G06F12/0866 ,  G06F12/109 ,  G06F2201/805 ,  G06F2201/82 ,  G06F2212/1032 ,  G06F2212/202 ,  G06F2212/2022 ,  G06F2212/222

Abstract: One embodiment provides for a data processing system comprising a multi-level system memory including a first memory level of volatile memory and a second memory level that is larger and slower in comparison with the first memory level. The second memory level includes non-volatile memory and can additionally include volatile memory. The multi-level system memory includes a multi-level memory controller including logic to manage a list of faulty addresses within the multi-level system memory. The multi-level memory controller can manage a list of faulty addresses. The multi-level memory controller is configured to satisfy a request for data stored in the first memory level from the second memory level when the data is stored in an address on the list of faulty addresses.

公开(公告)号：US20180004595A1

公开(公告)日：2018-01-04

申请号：US15201438

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Ashok Raj ,  Ron Gabor ,  Hisham Shafi ,  Sergiu Ghetie ,  Mohan J. Kumar ,  Theodros Yigzaw ,  Sarathy Jayakumar ,  Neeraj S. Upasani

IPC: G06F11/10 ,  G06F12/0893 ,  G06F12/1045 ,  G06F12/0875 ,  G06F3/06

CPC classification number: G06F11/1048 ,  G06F11/0721

Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.