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公开(公告)号：US11069118B2
公开(公告)日：2021-07-20
申请号：US16749856
申请日：2020-01-22
Applicant: INTEL CORPORATION
Inventor： Sven Woop , Attila Afra , Carsten Benthin , Ingo Wald , Johannes Guenther
Abstract: A graphics processing apparatus comprising bounding volume hierarchy (BVH) construction circuitry to perform a spatial analysis and temporal analysis related to a plurality of input primitives and responsively generate a BVH comprising spatial, temporal, and spatial-temporal components that are hierarchically arranged, wherein the spatial components include a plurality of spatial nodes with children, the spatial nodes bounding the children using spatial bounds, and the temporal components comprise temporal nodes with children, the temporal nodes bounding their children using temporal bounds and the spatial-temporal components comprise spatial-temporal nodes with children, the spatial-temporal nodes bounding their children using spatial and temporal bounds; and ray traversal/intersection circuitry to traverse a ray or a set of rays through the BVH in accordance with the spatial and temporal components.
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公开(公告)号：US20210097750A1
公开(公告)日：2021-04-01
申请号：US16585880
申请日：2019-09-27
Applicant: Intel Corporation
Inventor： Sven Woop , Prasoonkumar Surti , Karthik Vaidyanathan , Carsten Benthin , Joshua Barczak , Saikat Mandal
Abstract: An apparatus and method for merging primitives and coordinating between vertex and ray transformations on a shared transformation unit. For example, one embodiment of a graphics processor comprises: a queue comprising a plurality of entries; ordering circuitry/logic to order triangles front to back within the queue; pairing circuitry/logic to identify triangles in the queue sharing an edge and to merge the triangles sharing an edge to produce merged triangle pairs; and shared transformation circuitry to alternate between performing vertex transformations on vertices of the merged triangle pairs and to performing ray transformations on ray direction/origin data.
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公开(公告)号：US10929948B2
公开(公告)日：2021-02-23
申请号：US16236110
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Carsten Benthin , Prasoonkumar Surti , Karthik Vaidyanathan , Philip Laws , Scott Janus
IPC: G06T1/60 , G06T1/20 , G06F12/0862
Abstract: An apparatus and method for hardware page cache migration. For example, one embodiment of an apparatus comprises: a memory management unit (MMU) to manage memory page migration in multi-processor environments in which multiple processors share a virtual memory address space, the memory page migration comprising movement of one or more memory pages from a local memory of a first processor to a local memory of a second processor; a central page cache integral to or coupled to the MMU, the central page cache to store memory pages based on requests generated from one or more of the multiple processors; access pattern detection circuitry/logic to detect data access patterns associated with data access requests from one or more of the multiple processors; and an adaptive page prefetcher to prefetch one or more memory pages to the central page cache responsive to the access pattern detection circuitry/logic detecting one of the data access patterns.
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公开(公告)号：US10762668B2
公开(公告)日：2020-09-01
申请号：US16235672
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Carson Brownlee , Carsten Benthin , Joshua Barczak , Kai Xiao , Michael Apodaca , Prasoonkumar Surti , Thomas Raoux
Abstract: Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.
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公开(公告)号：US20200211152A1
公开(公告)日：2020-07-02
申请号：US16236110
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Carsten Benthin , Prasoonkumar Surti , Karthik Vaidyanathan , Philip Laws , Scott Janus
IPC: G06T1/60 , G06T1/20 , G06F12/0862
Abstract: An apparatus and method for hardware page cache migration. For example, one embodiment of an apparatus comprises: a memory management unit (MMU) to manage memory page migration in multi-processor environments in which multiple processors share a virtual memory address space, the memory page migration comprising movement of one or more memory pages from a local memory of a first processor to a local memory of a second processor; a central page cache integral to or coupled to the MMU, the central page cache to store memory pages based on requests generated from one or more of the multiple processors; access pattern detection circuitry/logic to detect data access patterns associated with data access requests from one or more of the multiple processors; and an adaptive page prefetcher to prefetch one or more memory pages to the central page cache responsive to the access pattern detection circuitry/logic detecting one of the data access patterns.
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Patent Agency Ranking
公开(公告)号：US10699370B1
公开(公告)日：2020-06-30
申请号：US16235604
申请日：2018-12-28
Applicant: Intel Corporation
Inventor： Karthik Vaidyanathan , Sven Woop , Carsten Benthin
Abstract: Apparatus and method for a compressed stack representation for a BVH. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a first graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; traversal/intersection circuitry to traverse one or more of the rays through the hierarchically arranged nodes of the BVH and intersect the one or more rays with primitives contained within the nodes; a short traversal stack of a fixed size comprising a specified number of entries fewer than the number of child nodes beneath the parent node, each entry associated with a child node at the current BVH level, the entries ordered from top to bottom within the short traversal stack based on a sorted distance of each respective child node, wherein each entry includes a field to indicate whether that entry is associated with a final child in the current BVH level; wherein the traversal/intersection circuitry is to process entries from the top of the traversal stack, removing entries as they are processed, the traversal/intersection circuitry to determine that a current entry is associated with the final child node at the current BVH level by reading a first value in the field.
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17.发明授权公开(公告)号：US10580197B2
公开(公告)日：2020-03-03
申请号：US16252414
申请日：2019-01-18
Applicant: Intel Corporation
Inventor： Ingo Wald , Gabor Liktor , Carsten Benthin , Carson Brownlee , Johannes Guenther , Jefferson D. Amstutz
Abstract: An apparatus and method for compressing ray tracing data prior to transmission between nodes. For example, one embodiment of an apparatus comprises: a first node comprising a first ray tracing engine, the first node communicatively coupled to a second node comprising a second ray tracing engine; first compression circuitry coupled to the first ray tracing engine, the first compression circuitry to perform compression on ray tracing data of the first ray tracing engine to produce a first compressed stream of ray tracing data; and interface circuitry to transmit the first compressed stream of ray tracing data from the first node to the second node.
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公开(公告)号：US10152822B2
公开(公告)日：2018-12-11
申请号：US15477019
申请日：2017-04-01
Applicant: Intel Corporation
Inventor： Prasoonkumar Surti , Karthik Vaidyanathan , Atsuo Kuwahara , Hugues Labbe , Sameer KP , Jonathan Kennedy , Joydeep Ray , Travis T. Schluessler , John H. Feit , Nikos Kaburlasos , Jacek Kwiatkowski , Tomer Bar-On , Carsten Benthin , Adam T. Lake , Vasanth Ranganathan , Abhishek R. Appu
Abstract: An embodiment of an electronic processing system may include an application processor, persistent storage media communicatively coupled to the application processor, a graphics subsystem communicatively coupled to the application processor, a sense engine communicatively coupled to the graphics subsystem to provide sensed information, a focus engine communicatively coupled to the sense engine and the graphics subsystem to provide focus information, a motion engine communicatively coupled to the sense engine, the focus engine, and the graphics subsystem to provide motion information, and a motion biased foveated renderer communicatively coupled to the motion engine, the focus engine, the sense engine to adjust one or more parameters of the graphics subsystem based on one or more of the sense information, the focus information, and the motion information. Other embodiments are disclosed and claimed.
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公开(公告)号：US11989815B2
公开(公告)日：2024-05-21
申请号：US17677118
申请日：2022-02-22
Applicant: INTEL CORPORATION
Inventor： Prasoonkumar Surti , Carsten Benthin , Karthik Vaidyanathan , Philip Laws , Scott Janus , Sven Woop
CPC classification number: G06T15/005 , G06T1/20 , G06T15/06 , G06T2210/52
Abstract: Cluster of acceleration engines to accelerate intersections. For example, one embodiment of an apparatus comprises: a set of graphics cores to execute a first set of instructions of a primary graphics thread; a scalar cluster comprising a plurality of scalar execution engines; and a communication fabric interconnecting the set of graphics cores and the scalar cluster; the set of graphics cores to offload execution of a second set of instructions associated with ray traversal and/or intersection operations to the scalar cluster; the scalar cluster comprising a plurality of local memories, each local memory associated with one of the scalar execution engines, wherein each local memory is to store a portion of a hierarchical acceleration data structure required by an associated scalar execution engine to execute one or more of the second set of instructions; the plurality of scalar execution engines to store results of the execution of the second set of instructions in a memory accessible by the set of graphics cores; wherein the set of graphics cores are to process the results within the primary graphics thread.
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公开(公告)号：US11922557B2
公开(公告)日：2024-03-05
申请号：US17746691
申请日：2022-05-17
Applicant: Intel Corporation
Inventor： Sven Woop , Prasoonkumar Surti , Karthik Vaidyanathan , Carsten Benthin , Joshua Barczak , Saikat Mandal
CPC classification number: G06T15/06 , G06T15/005 , G06T2210/21
Abstract: An apparatus and method for merging primitives and coordinating between vertex and ray transformations on a shared transformation unit. For example, one embodiment of a graphics processor comprises: a queue comprising a plurality of entries; ordering circuitry/logic to order triangles front to back within the queue; pairing circuitry/logic to identify triangles in the queue sharing an edge and to merge the triangles sharing an edge to produce merged triangle pairs; and shared transformation circuitry to alternate between performing vertex transformations on vertices of the merged triangle pairs and to performing ray transformations on ray direction/origin data.
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