公开(公告)号：US20230367740A1

公开(公告)日：2023-11-16

申请号：US18310129

申请日：2023-05-01

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Jorge Parra ,  Supratim Pal ,  Chandra Gurram

IPC: G06F15/80

CPC classification number: G06F15/8046 ,  G06F15/8007 ,  G06N20/00

Abstract: An apparatus to facilitate computing efficient cross channel operations in parallel computing machines using systolic arrays is disclosed. The apparatus includes a plurality of registers and one or more processing elements communicably coupled to the plurality of registers. The one or more processing elements include a systolic array circuit to perform cross-channel operations on source data received from a single source register of the plurality of registers, wherein the systolic array circuit is modified to: receive inputs from the single source register at different stages of the systolic array circuit; perform cross-channel operations at channels of the systolic array circuit; bypass disabled channels of the systolic array circuit, the disabled channels not used to compute the cross-channel operations; and broadcast a final result of a final stage of the systolic array circuit to all channels of a destination register.

公开(公告)号：US11636174B2

公开(公告)日：2023-04-25

申请号：US17527882

申请日：2021-11-16

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Jorge Parra ,  Supratim Pal ,  Ashutosh Garg ,  Shubra Marwaha ,  Chandra Gurram ,  Darin Starkey ,  Durgesh Borkar ,  Varghese George

IPC: G06F17/16 ,  G06F9/30 ,  G06F15/80

Abstract: Described herein is an accelerator device including a host interface, a fabric interconnect coupled with the host interface, and one or more hardware tiles coupled with the fabric interconnect, the one or more hardware tiles including sparse matrix multiply acceleration hardware including a systolic array with feedback inputs.

公开(公告)号：US20220414054A1

公开(公告)日：2022-12-29

申请号：US17304797

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Jorge Parra ,  Jiasheng Chen ,  Supratim Pal ,  Fangwen Fu ,  Sabareesh Ganapathy ,  Chandra Gurram ,  Chunhui Mei ,  Yue Qi

IPC: G06F15/80 ,  G06F9/38

Abstract: A processing apparatus described herein includes a general-purpose parallel processing engine comprising a systolic array having multiple pipelines, each of the multiple pipelines including multiple pipeline stages, wherein the multiple pipelines include a first pipeline, a second pipeline, and a common input shared between the first pipeline and the second pipeline.

公开(公告)号：US20220414053A1

公开(公告)日：2022-12-29

申请号：US17304678

申请日：2021-06-24

Applicant: Intel Corporation

Inventor： Jorge Parra ,  Wei-yu Chen ,  Kaiyu Chen ,  Varghese George ,  Junjie Gu ,  Chandra Gurram ,  Guei-Yuan Lueh ,  Stephen Junkins ,  Subramaniam Maiyuran ,  Supratim Pal

IPC: G06F15/80 ,  G06F9/50 ,  G06F9/54 ,  G06T1/20

Abstract: A processing apparatus includes a processing resource including a general-purpose parallel processing engine and a matrix accelerator. The matrix accelerator includes first circuitry to receive a command to perform operations associated with an instruction, second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction, third circuitry to read operands for the instruction from a register file associated with the systolic array, fourth circuitry to perform operations for the instruction via one or more passes through one or more physical pipeline stages of the systolic array based on a configuration performed by the second circuitry, and fifth circuitry to write output of the operations to the register file associated with the systolic array.

公开(公告)号：US20220413916A1

公开(公告)日：2022-12-29

申请号：US17358650

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Chandra Gurram ,  Wei-Yu Chen ,  Vikranth Vemulapalli ,  Subramaniam Maiyuran ,  Jorge Eduardo Parra Osorio ,  Shuai Mu ,  Guei-Yuan Lueh ,  Supratim Pal

IPC: G06F9/50 ,  G06F9/48 ,  G06T1/20

Abstract: Provision of multiple register allocation sizes for threads is described. An example of a system includes one or more processors including a graphics processor, the graphics processor including at least a first local thread dispatcher (TDL) and multiple processing resources, each processing resource including a plurality of registers; and memory for storage of data for processing, wherein the one or more processors are to determine a register size for a first thread; identify one or more processing resources having sufficient register space for the first thread; select a processing resource of the one or more processing resources having sufficient register space to assign the first thread; select an available thread slot of the selected processing resource for the first thread; and allocate registers of the selected processing resource for the first thread.

公开(公告)号：US20210365402A1

公开(公告)日：2021-11-25

申请号：US16900236

申请日：2020-06-12

Applicant: Intel Corporation

Inventor： Subramaniam Maiyuran ,  Jorge Parra ,  Supratim Pal ,  Chandra Gurram

IPC: G06F15/80

Abstract: An apparatus to facilitate computing efficient cross channel operations in parallel computing machines using systolic arrays is disclosed. The apparatus includes a plurality of registers and one or more processing elements communicably coupled to the plurality of registers. The one or more processing elements include a systolic array circuit to perform cross-channel operations on source data received from a single source register of the plurality of registers, the systolic array circuit modified to receive inputs from the single source register and route elements of the single source register to multiple channels in the systolic array circuit.

公开(公告)号：US10754651B2

公开(公告)日：2020-08-25

申请号：US16023713

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Chandra Gurram ,  Subramaniam Maiyuran ,  Buqi Cheng ,  Ashutosh Garg ,  Guei-Yuan Lueh ,  Wei-Yu Chen

IPC: G06F9/30 ,  G06T1/20 ,  G06T15/00 ,  G06F9/38

Abstract: Embodiments are generally directed to register bank conflict reduction for multi-threaded processor execution units. An embodiment of an apparatus includes a processor including one or more execution units (EUs), at least a first execution unit (EU) to process a plurality of threads, the first EU including a register file including multiple register banks with each register bank including multiple registers, and one or more read multiplexers to read registers from the register file, wherein attempting to read more than one register from a single register bank of the register file in a same clock cycle generates a register bank conflict. Registers for each thread for the first EU are distributed across the registers banks within the register file such that a first register for a first thread of the plurality of threads and a following second register for the first thread are located in different register banks within the register file.

公开(公告)号：US20200004534A1

公开(公告)日：2020-01-02

申请号：US16023713

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Chandra Gurram ,  Subramaniam Maiyuran ,  Buqi Cheng ,  Ashutosh Garg ,  Guei-Yuan Lueh ,  Wei-Yu Chen

IPC: G06F9/30 ,  G06F9/38 ,  G06T15/00 ,  G06T1/20

Abstract: Embodiments are generally directed to register bank conflict reduction for multi-threaded processor execution units. An embodiment of an apparatus includes a processor including one or more execution units (EUs), at least a first execution unit (EU) to process a plurality of threads, the first EU including a register file including multiple register banks with each register bank including multiple registers, and one or more read multiplexers to read registers from the register file, wherein attempting to read more than one register from a single register bank of the register file in a same clock cycle generates a register bank conflict. Registers for each thread for the first EU are distributed across the registers banks within the register file such that a first register for a first thread of the plurality of threads and a following second register for the first thread are located in different register banks within the register file.

公开(公告)号：US20250117360A1

公开(公告)日：2025-04-10

申请号：US18931412

申请日：2024-10-30

Applicant: Intel Corporation

Inventor： Jorge Parra ,  Wei-yu Chen ,  Kaiyu Chen ,  Varghese George ,  Junjie Gu ,  Chandra Gurram ,  Guei-Yuan Lueh ,  Stephen Junkins ,  Subramaniam Maiyuran ,  Supratim Pal

IPC: G06F15/80 ,  G06F9/30

Abstract: A processing apparatus includes a processing resource including a general-purpose parallel processing engine and a matrix accelerator. The matrix accelerator includes first circuitry to receive a command to perform operations associated with an instruction, second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction, third circuitry to read operands for the instruction from a register file associated with the systolic array, fourth circuitry to perform operations for the instruction via one or more passes through one or more physical pipeline stages of the systolic array based on a configuration performed by the second circuitry, and fifth circuitry to write output of the operations to the register file associated with the systolic array.

公开(公告)号：US20250117359A1

公开(公告)日：2025-04-10

申请号：US18913758

申请日：2024-10-11

Applicant: Intel Corporation

Inventor： Jorge Parra ,  Jiasheng Chen ,  Supratim Pal ,  Fangwen Fu ,  Sabareesh Ganapathy ,  Chandra Gurram ,  Chunhui Mei ,  Yue Qi

IPC: G06F9/38 ,  G06F9/30

Abstract: A processing apparatus described herein includes a general-purpose parallel processing engine comprising a systolic array having multiple pipelines, each of the multiple pipelines including multiple pipeline stages, wherein the multiple pipelines include a first pipeline, a second pipeline, and a common input shared between the first pipeline and the second pipeline.