-
公开(公告)号：US20250085969A1
公开(公告)日：2025-03-13
申请号：US18462832
申请日：2023-09-07
Applicant: Intel Corporation
Inventor： Shuai Mu , Supratim Pal , Pradeep Golconda , Srilakshmi Jammula , Jiasheng Chen
Abstract: An apparatus to facilitate unblocking the integer pipeline during math pipeline phases in a graphics environment is disclosed. The apparatus includes an execution resource comprising: a thread arbiter; a plurality of execution pipeline hardware circuitry comprising a math execution pipeline and an integer execution pipeline to share resources of the thread arbiter; arbitration hardware circuitry to determine whether the math execution pipeline is available for loading math operand data of a math instruction; and a math instruction staging buffer to store the math operand data responsive to the math execution pipeline not being available; wherein the integer execution pipeline is to receive integer operand data for an integer instruction while bypassing the math operand data in the math instruction staging buffer; and wherein the math execution pipeline is to receive, responsive to the math execution pipeline becoming available, the math operand data from the math instruction staging buffer.
-
公开(公告)号：US12067394B2
公开(公告)日：2024-08-20
申请号：US18170696
申请日：2023-02-17
Applicant: Intel Corporation
Inventor： Shuai Mu , Cristina S. Anderson , Subramaniam Maiyuran
CPC classification number: G06F9/3001 , G06F7/5443 , G06T1/20
Abstract: Embodiments are directed to systems and methods for reuse of FMA execution unit hardware logic to provide native support for execution of get exponent, get mantissa, and/or scale instructions within a GPU. These new instructions may be used to implement branch-free emulation algorithms for mathematical functions and analytic functions (e.g., transcendental functions) by detecting and handling various special case inputs within a pre-processing stage of the FMA execution unit, which allows the main dataflow of the FMA execution unit to be bypassed for such special cases. Since special cases are handled by the FMA execution unit, library functions emulating various functions, including, but not limited to logarithm, exponential, and division operations may be implemented with significantly fewer lines of machine-level code, thereby providing improved performance for HPC applications.
-
公开(公告)号：US12164884B2
公开(公告)日：2024-12-10
申请号：US17003334
申请日：2020-08-26
Applicant: Intel Corporation
Inventor： Shuai Mu , Cristina S. Anderson , Subramaniam Maiyuran
Abstract: Examples described herein relate to instructions to request performance of tanh and sigmoid instructions. For example, a compiler can generate native tanh instructions to perform tanh. In some examples, a tanh function can be compiled into instructions that include an instruction to perform either tanh(input) or tanh(input)/input depending on a value of the input to generate an intermediate output; an instruction to cause a performance of generation of scale factor based on the input; and an instruction to cause performance of a multiplication operation on the intermediate result with the scale factor. For example, a sigmoid function can be compiled to cause a math pipeline to perform a range check and performs operations based on a range.
-
公开(公告)号：US20220405096A1
公开(公告)日：2022-12-22
申请号：US17353984
申请日：2021-06-22
Applicant: Intel Corporation
Inventor： Shuai Mu , Cristina S. Anderson , Subramaniam Maiyuran
Abstract: Embodiments are directed to systems and methods for reuse of FMA execution unit hardware logic to provide native support for execution of get exponent, get mantissa, and/or scale instructions within a GPU. These new instructions may be used to implement branch-free emulation algorithms for mathematical functions and analytic functions (e.g., transcendental functions) by detecting and handling various special case inputs within a pre-processing stage of the FMA execution unit, which allows the main dataflow of the FMA execution unit to be bypassed for such special cases. Since special cases are handled by the FMA execution unit, library functions emulating various functions, including, but not limited to logarithm, exponential, and division operations may be implemented with significantly fewer lines of machine-level code, thereby providing improved performance for HPC applications.
-
公开(公告)号：US20250036412A1
公开(公告)日：2025-01-30
申请号：US18358308
申请日：2023-07-25
Applicant: Intel Corporation
Inventor： Supratim Pal , Jiasheng Chen , Christopher Spencer , Jorge E. Parra Osorio , Kevin Hurd , Guei-Yuan Lueh , Pradeep K. Golconda , Fangwen Fu , Wei Xiong , Hongzheng Li , James Valerio , Mukundan Swaminathan , Nicholas Murphy , Shuai Mu , Clifford Gibson , Buqi Cheng
Abstract: Described herein is a graphics processor comprising a memory interface and a graphics processing cluster coupled with the memory interface. The graphics processing cluster includes a plurality of processing resources. A processing resource of the plurality of processing resources includes a source crossbar communicatively coupled with a register file, the source crossbar to reorder data elements of a source operand and a format conversion pipeline to convert a plurality of input data elements specified by the source operand from a first format of a plurality of datatype formats to a second format of the plurality of datatype formats, the plurality of datatype formats including integer and floating-point formats.
-
Patent Agency Ranking
公开(公告)号：US20250036361A1
公开(公告)日：2025-01-30
申请号：US18358304
申请日：2023-07-25
Applicant: Intel Corporation
Inventor： Supratim Pal , Jiasheng Chen , Kevin Hurd , Jorge E. Parra Osorio , Christopher Spencer , Guei-Yuan Lueh , Pradeep K. Golconda , Fangwen Fu , Wei Xiong , Hongzheng Li , James Valerio , Mukundan Swaminathan , Nicholas Murphy , Shuai Mu , Clifford Gibson , Buqi Cheng
IPC: G06F7/483
Abstract: Described herein is a graphics processor comprising a memory interface and a graphics processing cluster coupled with the memory interface. The graphics processing cluster includes a multi-lane parallel floating-point unit and a multi-lane parallel integer unit. The multi-lane parallel integer unit includes an integer pipeline including a plurality of parallel integer logic units configured to perform integer compute operations on a plurality of input data elements and a format conversion pipeline including a plurality of parallel format conversion units configured to convert a plurality of input data elements from a first one of a plurality of datatype formats to a second one of the plurality of datatype formats, the plurality of datatype formats including integer and floating-point formats.
-
公开(公告)号：US12210905B2
公开(公告)日：2025-01-28
申请号：US17358650
申请日：2021-06-25
Applicant: Intel Corporation
Inventor： Chandra Gurram , Wei-Yu Chen , Vikranth Vemulapalli , Subramaniam Maiyuran , Jorge Eduardo Parra Osorio , Shuai Mu , Guei-Yuan Lueh , Supratim Pal
Abstract: Provision of multiple register allocation sizes for threads is described. An example of a system includes one or more processors including a graphics processor, the graphics processor including at least a first local thread dispatcher (TDL) and multiple processing resources, each processing resource including a plurality of registers; and memory for storage of data for processing, wherein the one or more processors are to determine a register size for a first thread; identify one or more processing resources having sufficient register space for the first thread; select a processing resource of the one or more processing resources having sufficient register space to assign the first thread; select an available thread slot of the selected processing resource for the first thread; and allocate registers of the selected processing resource for the first thread.
-
8.发明公开公开(公告)号：US20240103810A1
公开(公告)日：2024-03-28
申请号：US17935787
申请日：2022-09-27
Applicant: Intel Corporation
Inventor： Jiasheng Chen , Supratim Pal , Changwon Rhee , Hong Jiang , Kevin Hurd , Shuai Mu
CPC classification number: G06F7/5443 , G06F7/57 , G06F17/16
Abstract: An apparatus to facilitate supporting vector multiply add with double accumulator access in a graphics environment is disclosed. The apparatus includes a processor comprising processing resources, the processing resources comprising multiplier circuitry to: receive operands for a matrix multiplication operation, wherein the operands comprising two source matrices to be multiplied as part of the matrix multiplication operation; and issue a multiply and add vector (MADV) instruction for the multiplication operation utilizing a double accumulator access output, wherein the MADV instruction to multiply two vectors of the two source matrices in a single floating point (FP) pipeline of the processor.
-
公开(公告)号：US20250110741A1
公开(公告)日：2025-04-03
申请号：US18477790
申请日：2023-09-29
Applicant: Intel Corporation
Inventor： Jorge Eduardo Parra Osorio , Fangwen Fu , Guei-Yuan Lueh , Hong Jiang , Jiasheng Chen , Naveen K. Mellempudi , Kevin Hurd , Chunhui Mei , Alexandre Hadj-Chaib , Elliot Taylor , Shuai Mu
Abstract: An apparatus to facilitate supporting 8-bit floating point format for parallel computing and stochastic rounding operations in a graphics architecture is disclosed. The apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that is to operate on 8-bit floating point operands to perform a parallel dot product operation; a scheduler to schedule the decoded instruction and provide input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and circuitry to execute the decoded instruction to perform 32-way dot-product using 8-bit wide dot-product layers, each 8-bit wide dot-product layer comprises one or more sets of interconnected multipliers, shifters, and adders, wherein each set of multipliers, shifters, and adders is to generate a dot product of the 8-bit floating point operands.
-
公开(公告)号：US20240256274A1
公开(公告)日：2024-08-01
申请号：US18618648
申请日：2024-03-27
Applicant: Intel Corporation
Inventor： Naveen Mellempudi , Subramaniam Maiyuran , Varghese George , Fangwen Fu , Shuai Mu , Supratim Pal , Wei Xiong
CPC classification number: G06F9/30014 , G06F9/3818 , G06F9/4843 , G06F17/16 , G06N20/00
Abstract: An apparatus to facilitate supporting 8-bit floating point format operands in a computing architecture is disclosed. The apparatus includes a processor comprising: a decoder to decode an instruction fetched for execution into a decoded instruction, wherein the decoded instruction is a matrix instruction that operates on 8-bit floating point operands to cause the processor to perform a parallel dot product operation; a controller to schedule the decoded instruction and provide input data for the 8-bit floating point operands in accordance with an 8-bit floating data format indicated by the decoded instruction; and systolic dot product circuitry to execute the decoded instruction using systolic layers, each systolic layer comprises one or more sets of interconnected multipliers, shifters, and adder, each set of multipliers, shifters, and adders to generate a dot product of the 8-bit floating point operands.
-
-
-
-
-
-
-
-
-
Search Results
16
records
(took 0.027 seconds)
