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公开(公告)号：US20250103514A1
公开(公告)日：2025-03-27
申请号：US18974472
申请日：2024-12-09
Applicant: Intel Corporation
Inventor： Reshma Lal , Pradeep M. Pappachan , Luis Kida , Krystof Zmudzinski , Siddhartha Chhabra , Abhishek Basak , Alpa Narendra Trivedi , Anna Trikalinou , David M. Lee , Vedvyas Shanbhogue , Utkarsh Y. Kakaiya
IPC: G06F12/14 , G06F9/38 , G06F9/455 , G06F12/0802 , G06F21/57 , G06F21/60 , G06F21/64 , G06F21/76 , G06F21/79 , H04L9/06 , H04L9/08 , H04L9/32 , H04L41/046 , H04L41/28
Abstract: Technologies for secure device configuration and management include a computing device having an I/O device. A trusted agent of the computing device is trusted by a virtual machine monitor of the computing device. The trusted agent securely commands the I/O device to enter a trusted I/O mode, securely commands the I/O device to set a global lock on configuration registers, receives configuration data from the I/O device, and provides the configuration data to a trusted execution environment. In the trusted I/O mode, the I/O device rejects a configuration command if a configuration register associated with the configuration command is locked and the configuration command is not received from the trusted agent. The trusted agent may provide attestation information to the trusted execution environment. The trusted execution environment may verify the configuration data and the attestation information. Other embodiments are described and claimed.
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公开(公告)号：US12189542B2
公开(公告)日：2025-01-07
申请号：US17543267
申请日：2021-12-06
Applicant: Intel Corporation
Inventor： Reshma Lal , Pradeep M. Pappachan , Luis Kida , Krystof Zmudzinski , Siddhartha Chhabra , Abhishek Basak , Alpa Narendra Trivedi , Anna Trikalinou , David M. Lee , Vedvyas Shanbhogue , Utkarsh Y. Kakaiya
IPC: G06F12/14 , G06F9/38 , G06F9/455 , G06F12/0802 , G06F21/57 , G06F21/60 , G06F21/64 , G06F21/76 , G06F21/79 , H04L9/06 , H04L9/08 , H04L9/32 , H04L41/046 , H04L41/28
Abstract: Technologies for secure device configuration and management include a computing device having an I/O device. A trusted agent of the computing device is trusted by a virtual machine monitor of the computing device. The trusted agent securely commands the I/O device to enter a trusted I/O mode, securely commands the I/O device to set a global lock on configuration registers, receives configuration data from the I/O device, and provides the configuration data to a trusted execution environment. In the trusted I/O mode, the I/O device rejects a configuration command if a configuration register associated with the configuration command is locked and the configuration command is not received from the trusted agent. The trusted agent may provide attestation information to the trusted execution environment. The trusted execution environment may verify the configuration data and the attestation information. Other embodiments are described and claimed.
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公开(公告)号：US10884758B2
公开(公告)日：2021-01-05
申请号：US15640524
申请日：2017-07-01
Applicant: Intel Corporation
Inventor： Georges Manuel Faure Vaquero , John Cruz Mejia , Scott M. Rider , David M. Lee
Abstract: Aspects of the embodiments are directed to propagating an in-band hot reset through an add-in card compliant with a peripheral component interconnect express (PCIe) protocol. A host system can transmit an in-band hot reset to the add-in card across a link compliant with the PCIe protocol. A non-transparent bridge (NTB) on the add-in card can receive the in-band hot reset and reset configuration registers on the NTB. A system management controller can poll the NTB register values to determine that the polled configuration registers are different from expected values stored on an electrically erasable programmable random access memory (EEPROM). The SMC can signal a warm reset to a peripheral component based on the determination that the polled configuration register value is different from the expected register value.
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公开(公告)号：US10599178B2
公开(公告)日：2020-03-24
申请号：US16036419
申请日：2018-07-16
Applicant: Intel Corporation
Inventor： Michael C. Rifani , Alan B. Kyker , Alan S. Geist , David M. Lee
Abstract: Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.
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15.发明授权公开(公告)号：US09860173B2
公开(公告)日：2018-01-02
申请号：US14145376
申请日：2013-12-31
Applicant: Intel Corporation
Inventor： Jasmin Ajanovic , David Harriman , Blaise Fanning , David M. Lee
IPC: G06F15/16 , H04L12/801 , G06F13/12 , G06F13/38 , G06F13/42 , G06F13/40 , G06F5/06 , H04L12/835
CPC classification number: H04L47/10 , G06F5/06 , G06F13/124 , G06F13/385 , G06F13/4059 , G06F13/42 , G06F13/4221 , G06F13/4252 , G06F13/4265 , G06F13/4269 , G06F13/4282 , H04L47/30
Abstract: A storage device is provided to maintain a count of flow control credits to be granted to a device in association with transactions over a channel to be implemented on a data link and control logic is provided to communicate, to the device, an indication of an amount of flow control credits for the device in association with a reset of the data link.
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Patent Agency Ranking
公开(公告)号：US20250103397A1
公开(公告)日：2025-03-27
申请号：US18401399
申请日：2023-12-30
Applicant: Intel Corporation
Inventor： Andrew J. Herdrich , Daniel Joe , Filip Schmole , Philip Abraham , Stephen R. Van Doren , Priya Autee , Rajesh M. Sankaran , Anthony Luck , Philip Lantz , Eric Wehage , Edwin Verplanke , James Coleman , Scott Oehrlein , David M. Lee , Lee Albion , David Harriman , Vinit Mathew Abraham , Yi-Feng Liu , Manjula Peddireddy , Robert G. Blankenship
IPC: G06F9/50
Abstract: Techniques for quality of service (QoS) support for input/output devices and other agents are described. In embodiments, a processing device includes execution circuitry to execute a plurality of software threads; hardware to control monitoring or allocating, among the plurality of software threads, one or more shared resources; and configuration storage to enable the monitoring or allocating of the one or more shared resources among the plurality of software threads and one or more channels through which one or more devices are to be connected to the one or more shared resources.
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公开(公告)号：US20180276394A1
公开(公告)日：2018-09-27
申请号：US15470270
申请日：2017-03-27
Applicant: INTEL CORPORATION
Inventor： Mohan K. Nair , Rajesh M. Sankaran , Utkarsh Y. Kakaiya , Zhenfu Chai , David M. Lee , Pratik M. Marolia
IPC: G06F21/60 , H04L29/08 , G06F9/44 , G06F12/0811
CPC classification number: G06F21/602 , G06F9/4403 , G06F9/4406 , G06F9/4408 , G06F12/0815 , G06F13/4282 , G06F21/575 , G06F21/85 , G06F2212/1052 , G06F2213/0026 , H04L63/04
Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for extending a root complex to encompass an external component. A processor includes a processor core and root complex circuitry coupled to the processor core. The processor core is to execute a basic input/output system (BIOS) and an operating system (OS). The root complex circuitry includes a coherent interface port and a downstream port. The root complex circuitry is to couple to an external component via the downstream port and the coherent interface port. The BIOS, to extend a root complex beyond the root complex circuitry to encompass the external component, is to obfuscate the downstream port from the OS, define a virtual root bridge for the external component, and enable a security check at the external component to provide protection for the coherent interface port and the downstream port.
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公开(公告)号：US20220091998A1
公开(公告)日：2022-03-24
申请号：US17543267
申请日：2021-12-06
Applicant: Intel Corporation
Inventor： Reshma Lal , Pradeep M. Pappachan , Luis Kida , Krystof Zmudzinski , Siddhartha Chhabra , Abhishek Basak , Alpa Narendra Trivedi , Anna Trikalinou , David M. Lee , Vedvyas Shanbhogue , Utkarsh Y. Kakaiya
IPC: G06F12/14 , H04L9/32 , G06F21/76 , G06F21/60 , H04L9/08 , G06F9/455 , G06F21/57 , G06F21/64 , H04L12/24 , G06F21/79 , H04L9/06 , G06F9/38 , G06F12/0802
Abstract: Technologies for secure device configuration and management include a computing device having an I/O device. A trusted agent of the computing device is trusted by a virtual machine monitor of the computing device. The trusted agent securely commands the I/O device to enter a trusted I/O mode, securely commands the I/O device to set a global lock on configuration registers, receives configuration data from the I/O device, and provides the configuration data to a trusted execution environment. In the trusted I/O mode, the I/O device rejects a configuration command if a configuration register associated with the configuration command is locked and the configuration command is not received from the trusted agent. The trusted agent may provide attestation information to the trusted execution environment. The trusted execution environment may verify the configuration data and the attestation information. Other embodiments are described and claimed.
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公开(公告)号：US20190056761A1
公开(公告)日：2019-02-21
申请号：US16036419
申请日：2018-07-16
Applicant: Intel Corporation
Inventor： Michael C. Rifani , Alan B. Kyker , Alan S. Geist , David M. Lee
CPC classification number: G06F1/12 , G06F13/4291
Abstract: Some implementations disclosed herein provide techniques and arrangements for transferring data between asynchronous clock domains. A synchronization signal may be generated by a first of the clock domains, and data may be transferred between the domains in response to the synchronization signal. Clock cycles of the second of the clock domains may be monitored in comparison to the synchronization signal to report the number of second clock domain cycles occurring per occurrence of the synchronization signal. This information may be recorded by testing and validation equipment to facilitate error analyses.
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公开(公告)号：US20170294906A1
公开(公告)日：2017-10-12
申请号：US15632836
申请日：2017-06-26
Applicant: Intel Corporation
Inventor： Mahesh Wagh , Zuoguo J. Wu , Venkatraman Iyer , Gerald S. Pasdast , Todd A. Hinck , David M. Lee , Narasimha R. Lanka
CPC classification number: H03K5/26 , G01R31/041 , G06F1/3296 , G06F13/4291 , H03K5/131 , H03L9/00
Abstract: In an example, a system and method for centering in a high-performance interconnect (HPI) are disclosed. When an interconnect is powered up from a dormant state, it may be necessary to “center” the clock signal to ensure that data are read at the correct time. A multi-phase method may be used, in which a first phase comprises a reference voltage sweep to identify an optimal reference voltage. A second phase comprises a phase sweep to identify an optimal phase. A third sweep comprises a two-dimensional “eye” phase, in which a plurality of values within a two-dimensional eye derived from the first two sweeps are tested. In each case, the optimal value is the value that results in the fewest bit error across multiple lanes. In one example, the second and third phases are performed in software, and may include testing a “victim” lane, with adjacent “aggressor” lanes having a complementary bit pattern.
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