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    GALVANIC CORROSION PROTECTION FOR SEMICONDUCTOR PACKAGES
    12.
    发明申请
    GALVANIC CORROSION PROTECTION FOR SEMICONDUCTOR PACKAGES 审中-公开

    公开(公告)号：WO2019133006A1

    公开(公告)日：2019-07-04

    申请号：PCT/US2017/069136

    申请日：2017-12-30

    Applicant: INTEL CORPORATION ,  XU, Cheng ,  ZHAO, Junnan ,  PARK, Ji Yong ,  LEE, Kyu Oh

    Inventor： XU, Cheng ,  ZHAO, Junnan ,  PARK, Ji Yong ,  LEE, Kyu Oh

    IPC: H01L25/065 ,  H01L25/07 ,  H01L23/28 ,  H01L23/485

    Abstract: Techniques of protecting cored or coreless semiconductor packages having materials formed from dissimilar metals from galvanic corrosion are described. An exemplary semiconductor package comprises one or more build-up layers; first and second semiconductor components (e.g., die, EMIB, etc.) on or embedded in the one or more build-up layers. The first semiconductor component may be electrically coupled to the second semiconductor component via a contact pad and an interconnect structure that are formed in the one or more build-up layers. The contact pad can comprise a contact region, a non-contact region, and a gap region that separates the contact region from the non-contact region. Coupling of the contact pad and an interconnect structure is performed by coupling only the contact region with the interconnect structure. Also, a surface area of the contact region can be designed to substantially equal to a surface area of the interconnect structure.

    HIGH DENSITY PACKAGE SUBSTRATE FORMED WITH DIELECTRIC BI-LAYER
    13.
    发明申请
    HIGH DENSITY PACKAGE SUBSTRATE FORMED WITH DIELECTRIC BI-LAYER 审中-公开

    公开(公告)号：WO2018217188A1

    公开(公告)日：2018-11-29

    申请号：PCT/US2017/033897

    申请日：2017-05-23

    Applicant: INTEL CORPORATION

    Inventor： PIETAMBARAM, Srinivas V. ,  MANEPALLI, Rahul N. ,  UNRUH, David ,  TRUONG, Frank ,  LEE, Kyu Oh ,  ZHAO, Junnan ,  CHAVALI, Sri Chaitra Jyotsna

    IPC: H01L23/13 ,  H01L23/14

    Abstract: Disclosed herein are integrated circuit (IC) package substrates formed with a dielectric bi-layer, and related devices and methods. In some embodiments, an IC package substrate is fabricated by: forming a raised feature on a conductive layer; forming a dielectric bi-layer on the conductive layer, where the dielectric bi-layer includes a first sub-layer having a first material property and a second sub-layer having a second material property, and where the top surface of the second sub-layer is substantially planar with the top surface of the raised feature; and removing the first sub-layer until the second material property is detected to reveal the conductive feature. In some embodiments, an IC package substrate is fabricated by: forming a dielectric bi-layer on a patterned conductive layer, where the first sub-layer is less susceptible to removal than the second sub-layer; forming an opening in the dielectric bi-layer; etching; and forming a via having vertical sidewalls.

    TIN-ZINC MICROBUMP STRUCTURES AND METHOD OF MAKING SAME
    15.
    发明申请
    TIN-ZINC MICROBUMP STRUCTURES AND METHOD OF MAKING SAME 审中-公开
    锡锌微结构及其制造方法

    公开(公告)号：WO2018052601A1

    公开(公告)日：2018-03-22

    申请号：PCT/US2017/046769

    申请日：2017-08-14

    Applicant: INTEL CORPORATION

    Inventor： CHAVALI, Sri Chaitra J. ,  SCHUCKMAN, Amanda E. ,  LEE, Kyu Oh

    IPC: H01L23/532 ,  H01L25/07 ,  H01L23/00

    CPC classification number: H01L23/49816 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/17 ,  H01L2224/13111 ,  H01L2224/13118 ,  H01L2224/16238 ,  H01L2924/01022 ,  H01L2924/15321 ,  H01L2924/15747

    Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes a combination of tin and zinc that mitigates precipitation of residual copper by promoting the formation of miconstituents in the microbump. In another embodiment, the microbump has a mass fraction of zinc, or a mass fraction of tin, that is different in various regions along a height of the microbump.

    Abstract translation: 在集成电路封装衬底上提供与表面水平微凸块有效连接的技术和机制。 在一个实施例中，不同的金属被不同地电镀以形成延伸穿过衬底的表面级电介质到包括铜的种子层的微凸块。 微凸块包括锡和锌的组合，其通过促进微凸块中的微成分的形成来减轻残留铜的沉淀。 在另一个实施例中，微凸块的质量分数为锌或锡的质量分数，在沿着微凸块的高度的不同区域中是不同的。

    PACKAGE SUBSTRATE HAVING NONCIRCULAR INTERCONNECTS
    16.
    发明申请
    PACKAGE SUBSTRATE HAVING NONCIRCULAR INTERCONNECTS 审中-公开
    具有非公知相互连接的封装基板

    公开(公告)号：WO2017218074A1

    公开(公告)日：2017-12-21

    申请号：PCT/US2017/028433

    申请日：2017-04-19

    Applicant: INTEL CORPORATION

    Inventor： DARMAWIKARTA, Kristof Kuwawi ,  LEE, Kyu Oh ,  SOBIESKI, Daniel Nicholas

    IPC: H01L23/58 ,  H01L23/64 ,  H01L23/522 ,  H01L23/00

    Abstract: Package substrates including conductive interconnects having noncircular cross-sections, and integrated circuit packages incorporating such package substrates, are described. In an example, a conductive pillar having a noncircular pillar cross-section is electrically connected to an escape line routing layer. The escape line routing layer may include several series of conductive pads having noncircular pad cross-sections. Accordingly, conductive traces, e.g., strip line escapes and microstrip escapes, may be routed between the series of conductive pads in a single escape line routing layer.

    Abstract translation: 描述了包括具有非圆形横截面的导电互连的封装衬底以及包含这种封装衬底的集成电路封装。 在一个示例中，具有非圆形柱横截面的导电柱电连接到逃逸线路由层。 逃逸线布线层可以包括具有非圆形衬垫横截面的多个系列导电焊盘。 因此，导电迹线（例如，带状线逸出物和微带线逸出物）可以在单个逸出线路由层中的一系列导电垫之间布线。

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