公开(公告)号：WO2019221843A1

公开(公告)日：2019-11-21

申请号：PCT/US2019/026621

申请日：2019-04-09

Applicant: INTEL CORPORATION

Inventor： LEE, Kyu Oh ,  VADLAMANI, Sai ,  JAIN, Rahul ,  ZHAO, Junnan ,  PARK, Ji Yong ,  XU, Cheng ,  KIM, Seo Young

IPC: H01L23/29 ,  H01L23/31 ,  H01L23/00 ,  H01L23/525

Abstract: Techniques for fabricating a semiconductor package having magnetic materials embedded therein are described. For one technique, fabrication of package includes: forming a pad and a conductive line on a build-up layer; forming a raised pad structure on the build-up layer, the raised pad comprising a pillar structure on the pad; encapsulating the conductive line and the raised pad structure in a magnetic film comprising one or more magnetic fillers; planarizing a top surface of the magnetic film until top surfaces of the raised pad structure and the magnetic film are co-planar; depositing a primer layer on the top surfaces; removing one or more portions of the primer layer above the raised pad structure to create an opening; and forming a via in the opening on the raised pad structure.

公开(公告)号：WO2017160459A1

公开(公告)日：2017-09-21

申请号：PCT/US2017/018195

申请日：2017-02-16

Applicant: INTEL CORPORATION

Inventor： DARMAWIKARTA, Kristof ,  JAIN, Rahul ,  MAY, Robert Alan ,  LI, Sheng ,  BOYAPATI, Sri Ranga Sai

IPC: H01L21/3065 ,  H01L21/027 ,  H01L21/3213 ,  H01L21/225

CPC classification number: H05K3/0041 ,  H05K1/0313 ,  H05K1/09 ,  H05K3/0055 ,  H05K3/3452 ,  H05K2203/0502 ,  H05K2203/0548 ,  H05K2203/0562 ,  H05K2203/0588 ,  H05K2203/095

Abstract: A method of forming an electronic assembly. The method includes covering a patterned conductive layer that is on a dielectric layer with a solder resist; depositing a metal layer on to the solder resist; depositing a photo resist onto the metal layer; patterning the photo resist; etching the metal layer that is exposed from the photo resist to form a metal mask; removing the photo resist; and plasma etching the solder resist that is exposed from the metal mask. An electronic assembly for securing for an electronic card. The electronic assembly includes a patterned conductive layer that is on a dielectric layer; and a solder resist covering the patterned conductive layer and the dielectric layer, wherein the solder resist includes openings that expose the patterned conductive layer, wherein the openings in the solder resist only have organic material on side walls of the respective openings.

Abstract translation:

一种形成电子组件的方法。 该方法包括用阻焊剂覆盖介电层上的图案化导电层; 在所述阻焊剂上沉积金属层; 在所述金属层上沉积光刻胶; 构图光刻胶; 蚀刻从光致抗蚀剂暴露的金属层以形成金属掩模; 去除光刻胶; 并等离子蚀刻从金属掩模暴露的阻焊层。 用于电子卡安全保护的电子组件。 该电子组件包括位于电介质层上的图案化导电层; 以及覆盖图案化导电层和介电层的阻焊剂，其中阻焊剂包括暴露图案化导电层的开口，其中阻焊剂中的开口仅在各个开口的侧壁上具有有机材料。

公开(公告)号：WO2018125166A1

公开(公告)日：2018-07-05

申请号：PCT/US2016/069321

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： JAIN, Rahul ,  LEE, Kyu Oh ,  ALUR, Siddharth K. ,  JEN, Wei-Lun K. ,  MEHTA, Vipul V. ,  DHALL, Ashish ,  CHAVALI, Sri Chaitra J. ,  MANEPALLI, Rahul N. ,  ALUR, Amruthavalli P. ,  VADLAMANI, Sai

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/498 ,  H01L23/525 ,  H01L23/538 ,  H01L23/12 ,  H01L23/00 ,  H01L25/065

Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.

公开(公告)号：WO2017105388A1

公开(公告)日：2017-06-22

申请号：PCT/US2015/065511

申请日：2015-12-14

Applicant: INTEL CORPORATION

Inventor： MAY, Robert Alan ,  DARMAWIKARTA, Kristof ,  JAIN, Rahul ,  BOYAPATI, Sri Ranga Sai ,  MOUSSALLEM, Maroun ,  MANEPALLI, Rahul N. ,  PIETAMBARAM, Srinivas

IPC: G02B6/132

CPC classification number: G02B6/122 ,  G02B6/132 ,  G02B6/134

Abstract: This document discusses, among other things, a waveguide including a first metal having an outer surface proximate a dielectric material and an inner surface defining a path of the waveguide, a method of receiving an optical signal at the inner surface of the waveguide and transmitting the optical signal along at least a portion of the path of the waveguide. A method of integrating a waveguide in a substrate includes depositing sacrificial metal on a first surface of a carrier substrate to form a core of the waveguide, depositing a first metal over the sacrificial metal and at least a portion of the first surface of the carrier substrate, forming an outer surface of the waveguide and a conductor separate from the sacrificial metal, and depositing dielectric material over the first surface of the carrier substrate about the conductor.

Abstract translation: 该文献尤其讨论了一种波导，该波导包括第一金属和第二金属，该第一金属具有接近介电材料的外表面和限定波导的路径的内表面，在该接收器处接收光信号的方法 所述波导的内表面并且沿着所述波导的所述路径的至少一部分传输所述光信号。 一种将波导集成在衬底中的方法包括在载体衬底的第一表面上沉积牺牲金属以形成波导的核心，在牺牲金属上沉积第一金属以及载体衬底的第一表面的至少一部分 ，形成波导的外表面和与牺牲金属分开的导体，并且在载体衬底的第一表面上围绕导体沉积介电材料。

公开(公告)号：WO2018182652A1

公开(公告)日：2018-10-04

申请号：PCT/US2017/025199

申请日：2017-03-30

Applicant: INTEL CORPORATION

Inventor： VADLAMANI, Sai ,  ALEKSOV, Aleksandar ,  JAIN, Rahul ,  LEE, Kyu Oh ,  DARMAWIKARTA, Kristof Kuwawi ,  MAY, Robert Alan ,  BOYAPATI, Sri Ranga Sai ,  KAMGAING, Telesphor

IPC: H01L23/00 ,  H01L23/522

Abstract: Semiconductor packages having a first layer interconnect portion that includes a coaxial interconnect between a die and a package substrate are described. In an example, the package substrate includes a substrate-side coaxial interconnect electrically connected to a signal line. The die is mounted on the package substrate and includes a die-side coaxial interconnect coupled to the substrate-side coaxial interconnect. The coaxial interconnects can be joined by a solder bond between respective central conductors and shield conductors.

公开(公告)号：WO2018052600A1

公开(公告)日：2018-03-22

申请号：PCT/US2017/046745

申请日：2017-08-14

Applicant: INTEL CORPORATION

Inventor： JAIN, Rahul ,  LEE, Kyu Oh ,  SCHUCKMAN, Amanda E. ,  CHO, Steve S.

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/485

Abstract: Techniques and mechanisms for providing effective connectivity with surface level microbumps on an integrated circuit package substrate. In an embodiment, different metals are variously electroplated to form a microbump which extends through a surface-level dielectric of a substrate to a seed layer including copper. The microbump includes nickel and tin, wherein the nickel aids in mitigating an absorption of seed layer copper. In another embodiment, the microbump has a mass fraction of tin, or a mass fraction of nickel, that is different in various regions along a height of the microbump.

Abstract translation: 在集成电路封装衬底上提供与表面水平微凸块有效连接的技术和机制。 在一个实施例中，不同的金属被不同地电镀以形成延伸穿过衬底的表面级电介质到包括铜的种子层的微凸块。 微凸块包括镍和锡，其中镍有助于缓解晶种层铜的吸收。 在另一个实施例中，微凸块具有沿着微凸块的高度在不同区域中不同的锡质量分数或镍质量分数。

公开(公告)号：WO2020005559A1

公开(公告)日：2020-01-02

申请号：PCT/US2019/037021

申请日：2019-06-13

Applicant: INTEL CORPORATION

Inventor： XU, Cheng ,  JAIN, Rahul ,  KIM, Seo Young ,  LEE, Kyu Oh ,  PARK, Ji Yong ,  VADLAMANI, Sai ,  ZHAO, Junnan

IPC: H01G4/33 ,  H01G4/30

Abstract: Disclosed embodiments include an embedded thin-film capacitor and a magnetic inductor that are assembled in two adjacent build-up layers of a semiconductor package substrate. The thin-film capacitor is seated on a surface of a first of the build-up layers and the magnetic inductor is partially disposed in a recess in the adjacent build up layer. The embedded thin-film capacitor and the integral magnetic inductor are configured within a die shadow that is on a die side of the semiconductor package substrate.

公开(公告)号：WO2020005423A1

公开(公告)日：2020-01-02

申请号：PCT/US2019/033538

申请日：2019-05-22

Applicant: INTEL CORPORATION

Inventor： BROWN, Andrew J. ,  JAIN, Rahul ,  LI, Sheng ,  VADLAMANI, Sai ,  ZHANG, Chong

IPC: H01F17/00 ,  H01F5/00 ,  H01F27/28

Abstract: An apparatus and method of forming a magnetic inductor circuit. A substrate is provided and a first magnetic layer is formed in contact with one layer of the substrate. A conductive trace is formed in contact with the first magnetic layer. A sacrificial cooper layer protects the magnetic material from wet chemistry process steps. A conductive connection is formed from the conductive trace to the outside substrate, the conductive connection comprising a horizontal connection formed by in-layer plating. A second magnetic layer is formed in contact with the conductive trace. Instead of a horizontal connection, a vertical conductive connection can be formed that is perpendicular to the magnetic layers, by drilling a first via in a second of the magnetic layers, forming a buildup layer, and drilling a second via through the buildup layer, where the buildup layer protects the magnetic layers from wet chemistry processes.

公开(公告)号：EP3506347A1

公开(公告)日：2019-07-03

申请号：EP18209004.3

申请日：2018-11-28

Applicant: INTEL Corporation

Inventor： CHATTERJEE, Prithwish ,  ZHAO, Junnan ,  VADLAMANI, Sai ,  WANG, Ying ,  JAIN, Rahul ,  BROWN, Andrew J. ,  LINK, Lauren A. ,  XU, Cheng ,  LI, Sheng C.

IPC: H01L23/498 ,  H01L21/48

Abstract: Methods/structures of forming in-package inductor structures are described. Embodiments include a substrate including a dielectric material, the substrate having a first side and a second side. A conductive trace is located within the dielectric material. A first layer is on a first side of the conductive trace, wherein the first layer comprises an electroplated magnetic material, and wherein a sidewall of the first layer is adjacent the dielectric material. A second layer is on a second side of the conductive trace, wherein the second layer comprises the electroplated magnetic material, and wherein a sidewall of the second layer is adjacent the dielectric material.