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    VIA INTERCONNECTS IN SUBSTRATE PACKAGES
    2.
    发明申请
    VIA INTERCONNECTS IN SUBSTRATE PACKAGES 审中-公开
    威盛互联基础套件

    公开(公告)号：WO2017146737A1

    公开(公告)日：2017-08-31

    申请号：PCT/US2016/019943

    申请日：2016-02-26

    Applicant: INTEL CORPORATION

    Inventor： PIETAMBARAM, Srinivas V. ,  MANEPALLI, Rahul N.

    IPC: H01L23/48

    CPC classification number: H01L21/486 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L2221/68345

    Abstract: Embodiments herein may relate to providing, on a pad coupled with a carrier panel, a sacrificial element. Embodiments may further relate to providing, on the pad, a mold compound, wherein the mold compound is at least partially adjacent to the sacrificial element. Embodiments may further relate to removing, subsequent to the providing of the mold compound, the sacrificial element to form a via in the mold compound to at least partially expose the pad. Other embodiments may be described and/or claimed.

    Abstract translation: 这里的实施例可以涉及在与载体面板耦合的焊盘上提供牺牲元件。 实施例还可以涉及在垫上提供模制化合物，其中模制化合物至少部分地邻近牺牲元件。 实施例还可以涉及在提供模制化合物之后去除牺牲元件以在模制化合物中形成通孔以至少部分地暴露垫。 其他实施例可以被描述和/或要求保护。

    TECHNIQUES FOR DIE TILING
    4.
    发明申请
    TECHNIQUES FOR DIE TILING 审中-公开

    公开(公告)号：WO2019199428A1

    公开(公告)日：2019-10-17

    申请号：PCT/US2019/023666

    申请日：2019-03-22

    Applicant: INTEL CORPORATION

    Inventor： PIETAMBARAM, Srinivas V. ,  DUAN, Gang ,  KULKAMI, Deepak

    IPC: H01L23/528 ,  H01L23/522 ,  H01L23/14 ,  H01L25/065

    Abstract: Techniques are provided for fine node heterogeneous-chip packages. In an example, a method of making a heterogeneous-chip package can include coupling electrical terminals of a first side of a first base die to electrical terminals of a first side of a second base die using a silicon bridge, forming an organic substrate about the silicon bridge and adjacent the first sides of the first and second base dies, and coupling a fine node die to a second side of at least one of the first base die or the second base die.

    MICROELECTRONIC STRUCTURES INCLUDING GLASS CORES
    9.
    发明申请
    MICROELECTRONIC STRUCTURES INCLUDING GLASS CORES 审中-公开

    公开(公告)号：WO2022132267A1

    公开(公告)日：2022-06-23

    申请号：PCT/US2021/051692

    申请日：2021-09-23

    Applicant: INTEL CORPORATION

    Inventor： PIETAMBARAM, Srinivas V. ,  IBRAHIM, Tarek A. ,  DUAN, Gang ,  VADLAMANI, Sai ,  PENMECHA, Bharat Prasad

    IPC: H01L23/538 ,  H01L23/14

    Abstract: Disclosed herein are microelectronic structures including glass cores, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a glass core having through-glass vias (TGVs) therein; a metallization region at a first face of the glass core, wherein a conductive pathway in the first metallization region is conductively coupled to at least one of the TGVs; a bridge component in the metallization region; a first conductive contact at a face of the metallization region, wherein the first conductive contact is conductively coupled to the conductive pathway; and a second conductive contact at the face of the metallization region, wherein the second conductive contact is conductively coupled to the bridge component.

    SUBSTRATE EMBEDDED MAGNETIC CORE INDUCTORS
    10.
    发明申请
    SUBSTRATE EMBEDDED MAGNETIC CORE INDUCTORS 审中-公开

    公开(公告)号：WO2020005440A1

    公开(公告)日：2020-01-02

    申请号：PCT/US2019/034250

    申请日：2019-05-29

    Applicant: INTEL CORPORATION

    Inventor： PIETAMBARAM, Srinivas V. ,  DARMAWIKARTA, Kristof ,  DUAN, Gang ,  LI, Yonggang ,  PAITAL, Sameer

    IPC: H01F17/00 ,  H01F5/00 ,  H01F27/28

    Abstract: Described are microelectronic devices including an embedded microelectronic package for use as an integrated voltage regulator with a microelectronic system. The microelectronic package can include a substrate and a magnetic foil. The substrate can define at least one layer having one or more of electrically conductive elements separated by a dielectric material. The magnetic foil can have ferromagnetic alloy ribbons and can be embedded within the substrate adjacent to the one or more of electrically conductive elements. The magnetic foil can be positioned to interface with and be spaced from the one or more of electrically conductive element.

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