公开(公告)号：US20200264997A1

公开(公告)日：2020-08-20

申请号：US16778227

申请日：2020-01-31

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Rajesh M. Sankaran

IPC: G06F13/34

Abstract: Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.

公开(公告)号：US10657071B2

公开(公告)日：2020-05-19

申请号：US15714217

申请日：2017-09-25

Applicant: Intel Corporation

Inventor： David M. Durham ,  Siddhartha Chhabra ,  Amy L. Santoni ,  Gilbert Neiger ,  Barry E. Huntley ,  Hormuzd M. Khosravi ,  Baiju V. Patel ,  Ravi L. Sahita ,  Gideon Gerzon ,  Ido Ouziel ,  Ioannis T. Schoinas ,  Rajesh M. Sankaran

IPC: G06F12/14 ,  G06F21/60 ,  G06F21/82 ,  G06F3/06 ,  G06F21/53 ,  G06F21/78

Abstract: In one embodiment, a cryptographic circuit is adapted to receive a data line including at least an encrypted portion from a memory in response to a read request having a memory address from a first agent, obtain a key identifier for a key of the first agent from the data line, obtain the key using the key identifier, decrypt the at least encrypted portion of the data line using the key and send decrypted data of the at least encrypted portion of the data line to the first agent. Other embodiments are described and claimed.

公开(公告)号：US10346306B2

公开(公告)日：2019-07-09

申请号：US15089534

申请日：2016-04-02

Applicant: Intel Corporation

Inventor： Amitabha Roy ,  Subramanya R. Dulloor ,  Rajesh M. Sankaran

IPC: G06F12/08 ,  G06F12/10 ,  G06F12/0831 ,  G06F12/1027

Abstract: Methods and apparatuses relating to memory performance monitoring are described, including a processor and method for memory performance monitoring utilizing a monitor flag and first and second allocators for allocating virtual memory regions. In one embodiment, a processor includes at least one core, a performance monitoring unit, and a memory management unit including a first allocator to allocate a first virtual memory region of a memory for a first data structure, and a second allocator to allocate a second, different virtual memory region of the memory for a second data structure, wherein the memory management unit is to enable the performance monitoring unit to monitor a memory access request from the at least one core when a monitor flag is set for the first virtual memory region or the second, different virtual memory region, and a translation lookaside buffer (TLB) comprising a protection key for a page of a page table, wherein the is to translate a virtual address of the memory access request to a physical address and to set the monitor flag when the page includes the virtual address of the memory access request and the protection key indexes into a key register that indicates the virtual address of the memory access request is to be monitored, wherein the memory management unit is to append the monitor flag to the physical address.

公开(公告)号：US20190171396A1

公开(公告)日：2019-06-06

申请号：US16188950

申请日：2018-11-13

Applicant: Intel Corporation

Inventor： Subramanya R. Dulloor ,  Rajesh M. Sankaran ,  David A. Koufaty ,  Christopher J. Hughes ,  Jong Soo Park ,  Sheng Li

IPC: G06F3/06 ,  G06F9/50 ,  G06F12/0888

CPC classification number: G06F3/0673 ,  G06F3/0604 ,  G06F3/0608 ,  G06F3/0638 ,  G06F3/0665 ,  G06F9/50 ,  G06F12/023 ,  G06F12/08 ,  G06F12/0866 ,  G06F12/0888 ,  G06F12/1009 ,  G06F2212/60 ,  G06F2212/684

Abstract: A processor includes a processing core to generate a memory request for an application data in an application. The processor also includes a virtual page group memory management (VPGMM) unit coupled to the processing core to specify a caching priority (CP) to the application data for the application. The caching priority identifies importance of the application data in a cache.

公开(公告)号：US20190034367A1

公开(公告)日：2019-01-31

申请号：US15836854

申请日：2017-12-09

Applicant: Intel Corporation

Inventor： Utkarsh Kakaiya ,  Nagabhushan Chitlur ,  Rajesh M. Sankaran ,  Mohan Nair ,  Pratik M. Marolia

IPC: G06F13/20 ,  G06F13/40

Abstract: There is disclosed in one example an apparatus, including: a plurality of interconnects to communicatively couple an accelerator device to a host device; and an address translation module (ATM) to provide address mapping between host-physical address (HPA) and guest-physical address (GPA) spaces for the accelerator device, wherein the plurality of devices share a common GPA domain and wherein address mapping is to be associated with only one of the plurality of interconnects.

公开(公告)号：US09952987B2

公开(公告)日：2018-04-24

申请号：US14553430

申请日：2014-11-25

Applicant: Intel Corporation

Inventor： Jayakrishna Guddeti ,  Luke Chang ,  Rajesh M. Sankaran ,  Junaid F. Thaliyil

IPC: G06F13/24 ,  G06F12/0871

CPC classification number: G06F13/24 ,  G06F9/45558 ,  G06F9/4812 ,  G06F12/0871 ,  G06F2009/4557 ,  G06F2009/45579 ,  G06F2212/1032 ,  G06F2212/657

Abstract: An interrupt is identified from an input/output (I/O) device and an address of a particular cache line is identified associated with the interrupt. The cache line corresponds to a destination of the interrupt and represents one or more attributes of the interrupt. A request is sent to a coherency agent to acquire ownership of the particular cache line and a request is sent to perform a read-modify-write (RMW) operation on the cache line based on the interrupt.

公开(公告)号：US09921984B2

公开(公告)日：2018-03-20

申请号：US14581677

申请日：2014-12-23

Applicant: Intel Corporation

Inventor： Gilbert Neiger ,  Rajesh M. Sankaran

IPC: G06F13/34

CPC classification number: G06F13/34

Abstract: Systems and methods for delivering interrupts to user-level applications. An example processing system comprises: a memory configured to store a plurality of user-level APIC data structures and a plurality of user-level interrupt handler address data structures corresponding to a plurality of user-level applications being executed by the processing system; and a processing core configured, responsive to receiving a notification of a user-level interrupt, to: set a pending interrupt bit flag having a position defined by an identifier of the user-level interrupt in a user-level APIC data structure associated with a user-level application that is currently being executed by the processing core, and invoke a user-level interrupt handler identified by a user-level interrupt handler address data structure associated with the user-level application, for a pending user-level interrupt having a highest priority among one or more pending user-level interrupts identified by the user-level APIC data structure.

公开(公告)号：US20170286326A1

公开(公告)日：2017-10-05

申请号：US15088836

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Francesc Bernat Guim ,  David A. Koufaty ,  Andrea Pellegrini ,  Rajesh M. Sankaran

IPC: G06F12/14 ,  G06F21/62 ,  G06F12/10

CPC classification number: G06F12/1475 ,  G06F12/1009 ,  G06F12/1081 ,  G06F21/6209 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2212/152 ,  G06F2212/656 ,  G06F2212/657

Abstract: A processing system includes a processing core to execute a task and an input output (IO) memory management unit, coupled to the core. The IO memory management unit includes a storage unit to store a page table entry including an identifier of a memory domain and a protection key associated with the identifier. The protection key indicates whether a memory page in the memory domain is accessible. The IO memory management unit also includes a protection key register comprising a field indexed by the protection key, the field including a set of bits reflecting a memory access permission associated with the protection key. The protection key register is, responsive to receiving a request from an IO device to store data associated with the process or the thread of the process, to one of allow or deny permission to access the memory page in the memory domain for storage of the data associated with the process or the thread of the process based on the protection key.

公开(公告)号：US20170206177A1

公开(公告)日：2017-07-20

申请号：US14997478

申请日：2016-01-15

Applicant: Intel Corporation

Inventor： Jr-Shian Tsai ,  Ravi L. Sahita ,  Mesut A. Ergin ,  Rajesh M. Sankaran ,  Gilbert Neiger ,  Jun Nakajima ,  Edwin Verplanke ,  Barry E. Huntley ,  Tsung-Yuan C. Tai

IPC: G06F13/24 ,  G06F9/455

CPC classification number: G06F13/24 ,  G06F9/45558 ,  G06F2009/45575 ,  G06F2009/45579

Abstract: Embodiments of an invention interrupts between virtual machines are disclosed. In an embodiment, a processor includes an instruction unit and an execution unit, both implemented at least partially in hardware of the processor. The instruction unit is to receive an instruction to send an interrupt to a target virtual machine. The execution unit is to execute the instruction on a sending virtual machine without exiting the sending virtual machine. Execution of the instruction includes using a handle specified by the instruction to find a posted interrupt descriptor.

公开(公告)号：US09690716B2

公开(公告)日：2017-06-27

申请号：US14621654

申请日：2015-02-13

Applicant: Intel Corporation

Inventor： Sheng Li ,  Sanjay Kumar ,  Victor W. Lee ,  Rajesh M. Sankaran ,  Subramanya R. Dulloor

IPC: G06F12/08 ,  G06F12/1045 ,  G06F12/0891

CPC classification number: G06F12/1045 ,  G06F9/467 ,  G06F12/0891 ,  G06F12/1009 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1032 ,  G06F2212/152 ,  G06F2212/251 ,  G06F2212/69

Abstract: A processor includes a processing core to execute an application comprising instructions encoding a transaction with a persistent memory via a non-persistent cache, wherein the transaction is to create a mapping from a virtual address space to a memory region identified by a memory region identifier (MRID) in the persistent memory, and tag a cache line of the non-persistent cache with the MRID, in which the cache line is associated with a cache line status, and a cache controller, in response to detecting a failure event, to selectively evict contents of the cache line to the memory region identified by the MRID based on the cache line status.