公开(公告)号：US20220183157A1

公开(公告)日：2022-06-09

申请号：US17677851

申请日：2022-02-22

Applicant: INTEL CORPORATION

Inventor： Kristof Darmawikarta ,  Robert A. May ,  Yikang Deng ,  Ji Yong Park ,  Maroun D. Moussallem ,  Amruthavalli P. Alur ,  Sri Ranga Sai Boyapati ,  Lilia May

IPC: H05K1/18 ,  H05K1/11 ,  H05K3/42 ,  H05K3/46

Abstract: An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.

公开(公告)号：US11264307B2

公开(公告)日：2022-03-01

申请号：US16527961

申请日：2019-07-31

Applicant: Intel Corporation

Inventor： Aleksandar Aleksov ,  Hiroki Tanaka ,  Robert A. May ,  Kristof Darmawikarta ,  Changhua Liu ,  Chung Kwang Tan ,  Srinivas Pietambaram ,  Sri Ranga Sai Boyapati

IPC: H01L23/485 ,  H01L21/027 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48 ,  H01L23/544

Abstract: Techniques that can assist with fabricating a package layer that includes a plurality of dual-damascene zero-misalignment-vias (dual-damascene ZMVs) and a trace between the dual-damascene ZMVs are described. The disclosed techniques allow for the dual-damascene ZMVs and their corresponding trace to be plated simultaneously in a single step or operation. As such, there is little or no misalignment between the dual-damascene ZMVs, the trace, and the metal pads connected to the ZMVs. In this way, one or more of the embodiments described herein can assist with reducing manufacturing costs, reducing development time of fabricating a package layer, and with increasing the I/O density in a semiconductor package.

公开(公告)号：US11264239B2

公开(公告)日：2022-03-01

申请号：US16535618

申请日：2019-08-08

Applicant: Intel Corporation

Inventor： Hiroki Tanaka ,  Aleksandar Aleksov ,  Sri Ranga Sai Boyapati ,  Robert A. May ,  Kristof Darmawikarta

IPC: H01L21/027 ,  H01L23/00 ,  H01L23/485

Abstract: Techniques that can assist with fabricating a semiconductor package that includes a zero misalignment-via (ZMV) and/or a trace formed using a polarization process are described. The disclosed techniques can result in creation of ZMVs and/or traces between the ZMVs using a process comprising application of polarized light to one or more resist layers (e.g., a photoresist layer, etc.). One embodiment of a technique includes modulating an intensity of light applied to one or more resist layers by interaction of a light source with a photomask and at least one polarizer such that one or more patterns are created on the one or more resist layers. One embodiment of another technique includes creating patterns on one or more resist layers with different types of polarized light formed from a photomask and at least one polarizer. The disclosed techniques can assist with reducing manufacturing costs, reducing development time, and increasing I/O density.

公开(公告)号：US20210307172A1

公开(公告)日：2021-09-30

申请号：US16321420

申请日：2016-09-02

Applicant: INTEL CORPORATION

Inventor： Kristof Darmawikarta ,  Robert A. May ,  Yikang Deng ,  Ji Yong Park ,  Maroun D. Moussallem ,  Amruthavalli P. Alur ,  Sri Ranga Sai Boyapati ,  Lilia May

IPC: H05K1/18 ,  H05K3/46 ,  H05K1/11 ,  H05K3/42

Abstract: An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.

公开(公告)号：US20170362684A1

公开(公告)日：2017-12-21

申请号：US15674184

申请日：2017-08-10

Applicant: INTEL CORPORATION

Inventor： Robert A. May ,  Sri Ranga Sai Boyapati ,  Amruthavalli P. Alur ,  Daniel N. Sobieski

IPC: C22C9/00 ,  H01L23/498 ,  H01L23/12 ,  H01L23/49

CPC classification number: C22C9/00 ,  C22C27/04 ,  H01L23/12 ,  H01L23/49 ,  H01L23/49866 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0665

Abstract: Microelectronic substrates having copper alloy conductive routes to reduce warpage due to differing coefficient of thermal expansion of the components used to form the microelectronic substrates. In one embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper and an alloying metal of tungsten, molybdenum, or a combination thereof. In another embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper, an alloying metal of tungsten, molybdenum, or a combination thereof, and a co-deposition metal of nickel, cobalt, iron, or a combination thereof. In still another embodiment, the copper alloy conductive routes may have copper concentrations which are graded therethrough, which may enable better pattern formation during a subtractive etching process used to form the copper alloy conductive routes.

公开(公告)号：US09758845B2

公开(公告)日：2017-09-12

申请号：US14773108

申请日：2014-12-09

Applicant: Intel Corporation

Inventor： Robert A. May ,  Sri Ranga Sai Boyapati ,  Amruthavalli P. Alur ,  Daniel N. Sobieski

IPC: H05K1/09 ,  C22C9/00 ,  H01L23/12 ,  H01L23/49 ,  H01L23/498

CPC classification number: C22C9/00 ,  C22C27/04 ,  H01L23/12 ,  H01L23/49 ,  H01L23/49866 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81815 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/0665

Abstract: Microelectronic substrates having copper alloy conductive routes to reduce warpage due to differing coefficient of thermal expansion of the components used to form the microelectronic substrates. In one embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper and an alloying metal of tungsten, molybdenum, or a combination thereof. In another embodiment, the conductive routes of the microelectronic substrate may comprise an alloy of copper, an alloying metal of tungsten, molybdenum, or a combination thereof, and a co-deposition metal of nickel, cobalt, iron, or a combination thereof. In still another embodiment, the copper alloy conductive routes may have copper concentrations which are graded therethrough, which may enable better pattern formation during a subtractive etching process used to form the copper alloy conductive routes.

公开(公告)号：US09728500B2

公开(公告)日：2017-08-08

申请号：US14972936

申请日：2015-12-17

Applicant: Intel Corporation

Inventor： Siddharth K. Alur ,  Sri Chaitra J. Chavali ,  Robert A. May ,  Whitney M. Bryks

IPC: H01L23/52 ,  H01L23/528 ,  H01L21/768 ,  H01L21/3105 ,  H01L21/3205 ,  H01L21/02

CPC classification number: H01L23/528 ,  H01L21/02118 ,  H01L21/02164 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/31058 ,  H01L21/32051 ,  H01L21/321 ,  H01L21/76834 ,  H01L21/76841 ,  H01L23/53228 ,  H01L23/53295

Abstract: Embodiments of the present disclosure describe an integrated circuit and associated fabrication techniques and configurations, which may include forming on at least one of a metal layer or a polymer layer of an integrated circuit die a surface layer that includes an adhesion-functional group, and applying to the surface layer a next layer to adhere to the surface layer with the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a polymer layer, forming the surface layer may include copolymerizing on the polymer layer a polar monomer that includes the adhesion-functional group. In embodiments wherein the at least one of the metal layer or the polymer layer is a metal layer, forming the surface layer may include forming on the metal layer a self-assembled monolayer that includes amine group terminations. Other embodiments may be described and/or claimed.

公开(公告)号：US20240111090A1

公开(公告)日：2024-04-04

申请号：US17957341

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Robert A. May ,  Tarek Ibrahim ,  Shriya Seshadri ,  Kristof Darmawikarta ,  Hiroki Tanaka ,  Changhua Liu ,  Bai Nie ,  Lilia May ,  Srinivas Pietambaram ,  Zhichao Zhang ,  Duye Ye ,  Yosuke Kanaoka ,  Robin McRee

IPC: G02B6/12 ,  G02B6/13

CPC classification number: G02B6/12004 ,  G02B6/13 ,  G02B2006/12171

Abstract: A device comprises a substrate and an IC die, which may be a photonic IC. The substrate comprises a first surface, a second surface opposite the first surface, an optical waveguide integral with the substrate, and a hole extending from the first surface to the second surface. The hole comprises a first sidewall. The optical waveguide is between the first surface and the second surface, parallel to the first surface, and comprises a first end which extends to the first sidewall. The IC die is within the hole and comprises a second sidewall and an optical port at the second sidewall. The second sidewall is proximate to the first sidewall and the first end of the optical waveguide is proximate to and aligned with the optical port. The substrate may include a recess to receive another device comprising a socket.

公开(公告)号：US20240006327A1

公开(公告)日：2024-01-04

申请号：US17856663

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Aleksandar Aleksov ,  Kristof Darmawikarta ,  Robert A. May ,  Brandon Marin ,  Benjamin Duong ,  Suddhasattwa Nad ,  Hsin-Wei Wang ,  Leonel Arana ,  Darko Grujicic

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/5386 ,  H01L25/0655 ,  H01L23/49838 ,  H01L23/49822 ,  H01L23/49866 ,  H01L21/4857 ,  H01L21/486 ,  H01L24/08

Abstract: IC die package routing structures including a bulk layer of a first metal composition on an underlying layer of a second metal composition. The lower layer may be sputter deposited to a thickness sufficient to support plating of the bulk layer upon a first portion of the lower layer. Following the plating process, a second portion of the lower layer may be removed selectively to the bulk layer. Multiple IC die may be attached to the package with the package routing structures responsible for the transmission of high-speed data signals between the multiple IC die. The package may be further assembled to a host component that conveys power to the IC die package.

公开(公告)号：US20220130748A1

公开(公告)日：2022-04-28

申请号：US17567639

申请日：2022-01-03

Applicant: INTEL CORPORATION

Inventor： Sai Vadlamani ,  Prithwish Chatterjee ,  Robert A. May ,  Rahul S. Jain ,  Lauren A. Link ,  Andrew J. Brown ,  Kyu Oh Lee ,  Sheng C. Li

IPC: H01L23/498 ,  H01F17/00 ,  H01F41/04 ,  H05K1/00 ,  H01L23/00 ,  H01F27/28 ,  H01F27/40 ,  H01L21/48

Abstract: Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.