公开(公告)号：US20240111093A1

公开(公告)日：2024-04-04

申请号：US17957094

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Kristof Darmawikarta ,  Srinivas Venkata Ramanuja Pietambaram ,  Sandeep Gaan

IPC: G02B6/122 ,  G02B6/13

CPC classification number: G02B6/122 ,  G02B6/13

Abstract: Various embodiments disclosed relate to routing optical signals from silicon photonics, such as a photonic integrated circuit. The present disclosure includes a glass recirculatory layer with waveguides at varying heights to allow re-routing of such optical signals from silicon photonics, such as a photonic integrated circuit. Re-routing of optical signals can be accomplished in the glass recirculatory layer with reduced losses due to reduced intersections of waveguides therein.

公开(公告)号：US20240332100A1

公开(公告)日：2024-10-03

申请号：US18193172

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Pratyush Mishra ,  Marcel Wall ,  Sashi Kandanur ,  Pooya Tadayon ,  Srinivas Pietambaram ,  Benjamin Duong ,  Suddhasattwa Nad

IPC: H01L23/15 ,  H01F27/24 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522

CPC classification number: H01L23/15 ,  H01F27/24 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/5226

Abstract: Glass-integrated inductors in integrated circuit (IC) packages are disclosed. A disclosed IC package includes a glass layer having an aperture extending therethrough, and an inductor in the aperture, the inductor including a metal core extending through the aperture, the metal core electrically coupled to interconnects on opposite sides of the glass layer, and at least one of a ferrite or a magnetic alloy in the aperture and laterally surrounding the metal core.

公开(公告)号：US20240222018A1

公开(公告)日：2024-07-04

申请号：US18147503

申请日：2022-12-28

Applicant: Intel Corporation

Inventor： Thomas Sounart ,  Henning Braunisch ,  Aleksandar Aleksov ,  Kristof Darmawikarta ,  Numair Ahmed ,  Darko Grujicic ,  Suddhasattwa Nad ,  Benjamin Duong ,  Marcel Wall ,  Shayan Kaviani

IPC: H01G4/01 ,  H01G4/30 ,  H01G4/33 ,  H01L21/48 ,  H01L23/538

CPC classification number: H01G4/01 ,  H01G4/306 ,  H01G4/33 ,  H01L21/4846 ,  H01L23/5386 ,  H01L28/87 ,  H01L28/92 ,  H01G4/008

Abstract: Substrate package-integrated oxide capacitors and related methods are disclosed herein. An example apparatus including a first layer and a thin film capacitor including a second layer on the first layer, the second layer defining a plurality of openings and a third layer disposed on the first layer and in the plurality of openings, the second layer and the third layer corresponding to electrodes of a capacitor and a fourth layer disposed between the first layer and the second layer, the third layer including an oxidized material, the third layer forming a dielectric of the capacitor.

公开(公告)号：US20240113047A1

公开(公告)日：2024-04-04

申请号：US17957225

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Srinivasan Raman ,  Brandon C. Marin ,  Suddhasattwa Nad ,  Gang Duan ,  Benjamin Duong ,  Srinivas Venkata Ramanuja Pietambaram ,  Kripa Chauhan

IPC: H01L23/64

CPC classification number: H01L23/647 ,  H01L21/31105

Abstract: Various embodiments disclosed relate to embedded components in glass core layers for semiconductor assemblies. The present disclosure includes a semiconductor assembly with a glass core having one or more cavities and a component embedded into the glass core at the one or more cavities portion, the component at least partially embedded in the glass core, and a semiconductor die attached to the substrate.

公开(公告)号：US20240113046A1

公开(公告)日：2024-04-04

申请号：US17957257

申请日：2022-09-30

Applicant: Intel Corporation

Inventor： Jason Scott Steill ,  Shayan Kaviani ,  Srinivas Venkata Ramanuja Pietambaram ,  Suddhasattwa Nad ,  Benjamin Duong ,  Srinivasan Raman ,  Yi Yang

IPC: H01L23/62 ,  H01L21/48 ,  H01L23/00 ,  H01L23/15 ,  H01L23/498 ,  H01L23/64

CPC classification number: H01L23/62 ,  H01L21/486 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49844 ,  H01L23/49894 ,  H01L23/642 ,  H01L23/645 ,  H01L23/647 ,  H01L24/24 ,  H01L2224/24145 ,  H01L2924/12036

Abstract: Various embodiments disclosed relate to embedded components in glass core layers for semiconductor assemblies. The present disclosure includes a semiconductor assembly with a glass core having one or more cavities and a component embedded into the glass core at the one or more cavities portion, the component at least partially embedded in the glass core, and a semiconductor die attached to the substrate.

公开(公告)号：US20220093535A1

公开(公告)日：2022-03-24

申请号：US17029866

申请日：2020-09-23

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Roy Dittler ,  Darko Grujicic ,  Chandrasekharan Nair ,  Rengarajan Shanmugam

IPC: H01L23/64 ,  H01F27/32 ,  H01F27/28 ,  H01F27/24

Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.

公开(公告)号：US20250006671A1

公开(公告)日：2025-01-02

申请号：US18217123

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Marcel Arlan Wall ,  Hamid Azimi ,  Rahul N. Manepalli ,  Srinivas Venkata Ramanuja Pietambaram ,  Darko Grujicic ,  Steve Cho ,  Thomas L. Sounart ,  Gang Duan ,  Jung Kyu Han ,  Suddhasattwa Nad ,  Benjamin Duong ,  Shayan Kaviani

IPC: H01L23/00

Abstract: An intermediary layer, such as a dry deposition layer or a surface finish, is deposited on at least one exposed surface of surfaces within a layer of a semiconductor substrate. The intermediary layer is deposited on at least an electrically conductive material within a cavity in a layer. The intermediary layer is deposited using a chemical deposition process such as physical vapor deposition, chemical vapor deposition or sputtering.

公开(公告)号：US20240347402A1

公开(公告)日：2024-10-17

申请号：US18756679

申请日：2024-06-27

Applicant: Intel Corporation

Inventor： Jeremy Ecton ,  Brandon Christian Marin ,  Srinivas Venkata Ramanuja Pietambaram ,  Gang Duan ,  Leonel Arana ,  Benjamin Duong

IPC: H01L23/13 ,  H01L23/15 ,  H01L25/065

CPC classification number: H01L23/13 ,  H01L23/15 ,  H01L25/0655

Abstract: Methods and apparatus to reduce delamination in hybrid cores are disclosed. An example hybrid core of an integrated circuit (IC) package comprises a frame, and a glass panel including a top surface, an edge adjacent the frame, and a tapered surface extending between the edge and the top surface.

公开(公告)号：US20240345324A1

公开(公告)日：2024-10-17

申请号：US18133353

申请日：2023-04-11

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Kristof Darmawikarta ,  Soham Agarwal ,  Marcel Said ,  Sandeep Gaan

IPC: G02B6/26

CPC classification number: G02B6/26

Abstract: An integrated circuit package includes a substrate with an integrated circuit device mounting surface, and at least one optical fiber mount in the substrate. The optical fiber mount includes a support having at least one optical fiber mounting channel, and the optical fiber mounting channel is configured to mount at least one clad optical fiber.

公开(公告)号：US20240331921A1

公开(公告)日：2024-10-03

申请号：US18739049

申请日：2024-06-10

Applicant: Intel Corporation

Inventor： Benjamin Duong ,  Michael Garelick ,  Darko Grujicic ,  Tarek Ibrahim ,  Brandon C. Marin ,  Sai Vadlamani ,  Marcel Wall

IPC: H01F27/28 ,  H01F41/32 ,  H01L23/498 ,  H01L23/64

CPC classification number: H01F27/2804 ,  H01F41/32 ,  H01L23/49827 ,  H01L23/645 ,  H01F2027/2809 ,  H01L23/49816

Abstract: An electronic substrate may be fabricated by forming a base substrate and forming an inductor extending through the base substrate, wherein the inductor includes a magnetic material layer and a barrier layer, such that the barrier layer prevents the magnetic material layer from leaching into plating solutions during the fabrication of the electronic substrate. In one embodiment, the barrier material may comprise titanium. In another embodiment, the barrier layer may comprise a polymeric material. In still another embodiment, the barrier layer may comprise a nitride material layer. The inductor may further include a plating seed layer on the barrier layer and a conductive fill material abutting the plating seed layer.