公开(公告)号：WO2020190800A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/022838

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： RAY, Joydeep ,  COORAY, Niranjan ,  MAIYURAN, Subramaniam ,  KOKER, Altug ,  SURTI, Prasoonkumar ,  GEORGE, Varghese ,  ANDREI, Valentin ,  APPU, Abhishek ,  GARCIA, Guadalupe ,  K, Pattabhiraman ,  KIM, SungYe ,  KUMAR, Sanjay ,  MAROLIA, Pratik ,  OULD-AHMED-VALL, Elmoustapha ,  RANGANATHAN, Vasanth ,  SADLER, William ,  STRIRAMASSARMA, Lakshminarayanan

IPC: G06F12/0804 ,  G06F12/0893 ,  G06F12/0862 ,  G06F9/38 ,  G06F12/12 ,  G06F12/128

Abstract: Embodiments described herein provide techniques to enable the dynamic reconfiguration of memory on a general-purpose graphics processing unit. One embodiment described herein enables dynamic reconfiguration of cache memory bank assignments based on hardware statistics. One embodiment enables for virtual memory address translation using mixed four kilobyte and sixty-four kilobyte pages within the same page table hierarchy and under the same page directory. One embodiment provides for a graphics processor and associated heterogenous processing system having near and far regions of the same level of a cache hierarchy.

公开(公告)号：WO2020190432A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/017996

申请日：2020-02-12

Applicant: INTEL CORPORATION ,  SURTI, Prasoonkumar ,  HUNTER, Arthur ,  SINHA, Kamal ,  JANUS, Scott ,  INSKO, Brent ,  RANGANATHAN, Vasanth ,  STRIRAMASSARMA, Lakshminarayanan

Inventor： SURTI, Prasoonkumar ,  HUNTER, Arthur ,  SINHA, Kamal ,  JANUS, Scott ,  INSKO, Brent ,  RANGANATHAN, Vasanth ,  STRIRAMASSARMA, Lakshminarayanan

IPC: G06T15/00

Abstract: Embodiments are generally directed to multi-tile graphics processor rendering. An embodiment of an apparatus includes a memory for storage of data; and one or more processors including a graphics processing unit (GPU) to process data, wherein the GPU includes a plurality of GPU tiles, wherein, upon geometric data being assigned to each of a plurality of screen tiles, the apparatus is to transfer the geometric data to the plurality of GPU tiles.

公开(公告)号：WO2016003544A1

公开(公告)日：2016-01-07

申请号：PCT/US2015/030513

申请日：2015-05-13

Applicant: INTEL CORPORATION

Inventor： KOKER, Altug ,  STRIRAMASSARMA, Lakshminarayanan ,  ALI, Akif

IPC: G06T1/20

CPC classification number: G06T1/20 ,  G06F15/08 ,  G06T1/60 ,  G06T11/001 ,  G06T15/005 ,  G06T15/80 ,  H04L49/109

Abstract: In on embodiment, a hybrid fabric interconnects multiple graphics processor cores within a processor. The hybrid fabric interconnect includes multiple data channels, including programmable virtual data channels. The virtual data channels carry multiple traffic classes of packet-based messages. The virtual data channels and multiple traffic classes may be assigned one of multiple priorities. The virtual data channels may be arbitrated independently. The hybrid fabric is scalable and can support multiple topologies, including multiple stacked integrated circuit topologies.

Abstract translation: 在实施例中，混合架构互连处理器内的多个图形处理器核心。 混合网络互连包括多个数据信道，包括可编程虚拟数据信道。 虚拟数据信道承载多个基于分组的消息的业务类别。 可以将虚拟数据信道和多个业务类别分配为多个优先级之一。 虚拟数据通道可以独立地进行仲裁。 混合架构是可扩展的，可以支持多种拓扑结构，包括多个堆叠集成电路拓扑。

公开(公告)号：WO2020190813A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/022851

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： APPU, Abhishek ,  STRIRAMASSARMA, Lakshminarayanan ,  KOKER, Altug ,  COLEMAN, Sean ,  GEORGE, Varghese ,  HUNTER, JR., Arthur ,  INSKO, Brent ,  JANUS, Scott ,  OULD-AHMED-VALL, Elmoustapha ,  RANGANATHAN, Vasanth ,  RAY, Joydeep ,  SINHA, Kamal ,  SURTI, Prasoonkumar ,  VAIDYANATHAN, Karthik

IPC: G06F12/12 ,  G06F12/128 ,  G06F12/0886 ,  G06F12/0862 ,  G06F9/38

Abstract: Graphics processors of the present design provide hierarchical open sectors and variable cache sizes for cache operations. In one embodiment, a graphics processor comprises a cache memory having a hierarchical open sector design including a first hierarchy of upper and lower regions with each region including a second hierarchy of sectors. A cache controller is configured to initially open a first sector of the lower region, to receive a memory request that does not match an address in the first sector, and to open a second sector of the lower region.

公开(公告)号：WO2020190811A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/022849

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： KOKER, Altug ,  STRIRAMASSARMA, Lakshminarayanan ,  ANANTARAMAN, Aravindh ,  ANDREI, Valentin ,  APPU, Abhishek R. ,  COLEMAN, Sean ,  GEORGE, Varghese ,  K, Pattabhiraman ,  MACPHERSON, Mike ,  MAIYURAN, Subramaniam ,  OULD-AHMED-VALL, ElMoustapha ,  RANGANATHAN, Vasanth ,  RAY, Joydeep ,  S, Jayakrishna P ,  SURTI, Prasoonkumar

IPC: G06F9/38 ,  G06F12/0862 ,  G06F9/30

Abstract: Embodiments are generally directed to cache structure and utilization. An embodiment of an apparatus includes one or more processors including a graphics processor; a memory for storage of data for processing by the one or more processors; and a cache to cache data from the memory; wherein the apparatus is to provide for dynamic overfetching of cache lines for the cache, including receiving a read request and accessing the cache for the requested data, and upon a miss in the cache, overfetching data from memory or a higher level cache in addition to fetching the requested data, wherein the overfetching of data is based at least in part on a current overfetch boundary, and provides for data is to be prefetched extending to the current overfetch boundary.

公开(公告)号：WO2020190807A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/022845

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： SURTI, Prasoonkumar ,  MAIYURAN, Subramaniam ,  ANDREI, Valentin ,  APPU, Abhishek ,  GEORGE, Varghese ,  KOKER, Altug ,  MACPHERSON, Mike ,  OULD-AHMED-VALL, Elmoustapha ,  RANGANATHAN, Vasanth ,  RAY, Joydeep ,  STRIRAMASSARMA, Lakshminarayanan ,  KIM, SungYe

IPC: G06F9/30

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides techniques to optimize training and inference on a systolic array when using sparse data. One embodiment provides techniques to use decompression information when performing sparse compute operations. One embodiment enables the disaggregation of special function compute arrays via a shared reg file. One embodiment enables packed data compress and expand operations on a GPGPU. One embodiment provides techniques to exploit block sparsity within the cache hierarchy of a GPGPU.

公开(公告)号：WO2020190796A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/022833

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： KOKER, Altug ,  RAY, Joydeep ,  OULD-AHMED-VALL, Elmoustapha ,  APPU, Abhishek ,  ANANTARAMAN, Aravindh ,  ANDREI, Valentin ,  BILAGI, Durgaprasad ,  GEORGE, Varghese ,  INSKO, Brent ,  JAHAGIRDAR, Sanjeev ,  JANUS, Scott ,  K, Pattabhiraman ,  KIM, SungYe ,  MAIYURAN, Subramaniam ,  RANGANATHAN, Vasanth ,  STRIRAMASSARMA, Lakshminarayanan ,  TIAN, Xinmin

IPC: G06F9/38 ,  G06F12/0862 ,  G06F9/30 ,  G06F12/123 ,  G06F12/126

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received.

公开(公告)号：WO2020190429A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/017897

申请日：2020-02-12

Applicant: INTEL CORPORATION ,  VEMULAPALLI, Vikranth ,  STRIRAMASSARMA, Lakshminarayanan ,  MACPHERSON, Mike ,  ANANTARAMAN, Aravindh ,  ASHBAUGH, Ben ,  RAMADOSS, Murali ,  SADLER, William B. ,  PEARCE, Jonathan ,  JANUS, Scott ,  INSKO, Brent ,  RANGANATHAN, Vasanth ,  SINHA, Kamal ,  HUNTER, Arthur ,  SURTI, Prasoonkumar ,  GALOPPO VON BORRIES, Nicolas ,  RAY, Joydeep ,  APPU, Abhisek R. ,  OULD-AHMED-VALL, ElMoustapha ,  KOKER, Altug ,  KIM, Sungye ,  MAIYURAN, Subramaniam ,  ANDREI, Valentin

Inventor： VEMULAPALLI, Vikranth ,  STRIRAMASSARMA, Lakshminarayanan ,  MACPHERSON, Mike ,  ANANTARAMAN, Aravindh ,  ASHBAUGH, Ben ,  RAMADOSS, Murali ,  SADLER, William B. ,  PEARCE, Jonathan ,  JANUS, Scott ,  INSKO, Brent ,  RANGANATHAN, Vasanth ,  SINHA, Kamal ,  HUNTER, Arthur ,  SURTI, Prasoonkumar ,  GALOPPO VON BORRIES, Nicolas ,  RAY, Joydeep ,  APPU, Abhisek R. ,  OULD-AHMED-VALL, ElMoustapha ,  KOKER, Altug ,  KIM, Sungye ,  MAIYURAN, Subramaniam ,  ANDREI, Valentin

IPC: G06F12/0862 ,  G06F12/0897 ,  G06F12/0888 ,  G06F9/38

Abstract: Embodiments are generally directed to data prefetching for graphics data processing. An embodiment of an apparatus includes one or more processors including one or more graphics processing units (GPUs); and a plurality of caches to provide storage for the one or more GPUs, the plurality of caches including at least an L1 cache and an L3 cache, wherein the apparatus to provide intelligent prefetching of data by a prefetcher of a first GPU of the one or more GPUs including measuring a hit rate for the L1 cache; upon determining that the hit rate for the L1 cache is equal to or greater than a threshold value, limiting a prefetch of data to storage in the L3 cache, and upon determining that the hit rate for the L1 cache is less than a threshold value, allowing the prefetch of data to the L1 cache.

公开(公告)号：EP4283950A2

公开(公告)日：2023-11-29

申请号：EP23202085.9

申请日：2015-05-13

Applicant: INTEL Corporation

Inventor： KOKER, Altug ,  STRIRAMASSARMA, Lakshminarayanan ,  ALI, Akif

IPC: H04L49/109

Abstract: In on embodiment, a hybrid fabric interconnects multiple graphics processor cores within a processor. The hybrid fabric interconnect includes multiple data channels, including programmable virtual data channels. The virtual data channels carry multiple traffic classes of packet-based messages. The virtual data channels and multiple traffic classes may be assigned one of multiple priorities. The virtual data channels may be arbitrated independently. The hybrid fabric is scalable and can support multiple topologies, including multiple stacked integrated circuit topologies.

公开(公告)号：EP3938893A1

公开(公告)日：2022-01-19

申请号：EP20718900.2

申请日：2020-03-14

Applicant: INTEL Corporation

Inventor： KOKER, Altug ,  RAY, Joydeep ,  OULD-AHMED-VALL, Elmoustapha ,  APPU, Abhishek ,  ANANTARAMAN, Aravindh ,  ANDREI, Valentin ,  BILAGI, Durgaprasad ,  GEORGE, Varghese ,  INSKO, Brent ,  JAHAGIRDAR, Sanjeev ,  JANUS, Scott ,  K, Pattabhiraman ,  KIM, SungYe ,  MAIYURAN, Subramaniam ,  RANGANATHAN, Vasanth ,  STRIRAMASSARMA, Lakshminarayanan ,  TIAN, Xinmin

IPC: G06F9/38 ,  G06F12/0862 ,  G06F9/30 ,  G06F12/123 ,  G06F12/126