公开(公告)号：WO2022271226A1

公开(公告)日：2022-12-29

申请号：PCT/US2022/020408

申请日：2022-03-15

Applicant: INTEL CORPORATION

Inventor： PARRA, Jorge ,  FU, Fangwen ,  MAIYURAN, Subramaniam ,  GEORGE, Varghese ,  MACPHERSON, Mike ,  PAL, Supratim ,  GURRAM, Chandra ,  GANAPATHY, Sabareesh ,  AVANCHA, Sasikanth ,  VOOTURI, Dharma Teja ,  MELLEMPUDI, Naveen ,  DAS, Dipankar

IPC: G06F17/16 ,  G06F9/00 ,  G06F15/8046 ,  G06F7/523 ,  G06F7/5443 ,  G06F9/3001 ,  G06F9/30036

Abstract: A processing apparatus is described herein that includes a general-purpose parallel processing engine comprising a matrix accelerator including one or more systolic arrays, at least one of the one or more systolic arrays comprising multiple pipeline stages, each pipeline stage of the multiple pipeline stages including multiple processing elements, the multiple processing elements configured to perform processing operations on input matrix elements based on output sparsity metadata. The output sparsity metadata indicates to the multiple processing elements to bypass multiplication for a first row of elements of a second matrix and multiply a second row of elements of the second matrix with a column of matrix elements of a first matrix.

公开(公告)号：WO2020190810A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/022848

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： KOKER, Altug ,  ASHBAUGH, Ben ,  JANUS, Scott ,  ANANTARAMAN, Aravindh ,  APPU, Abhishek R. ,  COORAY, Niran ,  GEORGE, Varghese ,  HUNTER, Arthur ,  INSKO, Brent ,  OULD-AHMED-VALL, ElMoustapha ,  PANNEER, Selvakumar ,  RANGANATHAN, Vasanth ,  RAY, Joydeep ,  SINHA, Kamal ,  STRIRAMASSARMA, Lakshminarayanan ,  SURTI, Prasoonkumar ,  TANGRI, Saurabh

IPC: G06F12/0804 ,  G06F12/0893 ,  G06F15/173

Abstract: Embodiments are generally directed to a multi-tile architecture for graphics operations. An embodiment of an apparatus includes a multi-tile architecture for graphics operations including a multi-tile graphics processor, the multi-tile processor includes one or more dies; multiple processor tiles installed on the one or more dies; and a structure to interconnect the processor tiles on the one or more dies, wherein the structure to enable communications between processor tiles the processor tiles.

公开(公告)号：WO2020190799A2

公开(公告)日：2020-09-24

申请号：PCT/US2020/022837

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： KOKER, Altug ,  RAY, Joydeep ,  ASHBAUGH, Ben ,  PEARCE, Jonathan ,  APPU, Abhishek ,  RANGANATHAN, Vasanth ,  STRIRAMASSARMA, Lakshminarayanan ,  OULD-AHMED-VALL, Elmoustapha ,  ANANTARAMAN, Aravindh ,  ANDREI, Valentin ,  GALOPPO VON BORRIES, Nicolas ,  GEORGE, Varghese ,  HAREL, Yoav ,  HUNTER, Arthur Jr. ,  INSKO, Brent ,  JANUS, Scott ,  K, Pattabhiraman ,  MACPHERSON, Mike ,  MAIYURAN, Subramaniam ,  PETRE, Marian Alin ,  RAMADOSS, Murali ,  SHAH, Shailesh ,  SINHA, Kamal ,  SURTI, Prasoonkumar ,  VEMULAPALLI, Vikranth

IPC: G06F9/38 ,  G06F12/0862 ,  G06F9/30 ,  G06F12/02 ,  G06F12/06 ,  G06F12/0804 ,  G06F12/0893 ,  G06F12/12 ,  G06F12/128 ,  G06F15/173 ,  G06F9/50

Abstract: Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

公开(公告)号：WO2020190798A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/022836

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： STRIRAMASSARMA, Lakshminarayanan ,  SURTI, Prasoonkumar ,  GEORGE, Varghese ,  ASHBAUGH, Ben ,  ANANTARAMAN, Aravindh ,  ANDREI, Valentin ,  APPU, Abhishek ,  GALOPPO VON BORRIES, Nicolas ,  KOKER, Altug ,  MACPHERSON, Mike ,  MAIYURAN, Subramaniam ,  MISTRY, Nilay ,  OULD-AHMED-VALL, Elmoustapha ,  PANNEER, Selvakumar ,  RANGANATHAN, Vasanth ,  RAY, Joydeep ,  SHAH, Ankur ,  TANGRI, Saurabh

IPC: G06F9/38 ,  G06F12/0862 ,  G06F9/30

Abstract: Multi-tile Memory Management for Detecting Cross Tile Access, Providing Multi-Tile Inference Scaling with multicasting of data via copy operation, and Providing Page Migration are disclosed herein. In one embodiment, a graphics processor for a multi-tile architecture includes a first graphics processing unit (GPU) having a memory and a memory controller, a second graphics processing unit (GPU) having a memory and a cross-GPU fabric to communicatively couple the first and second GPUs. The memory controller is configured to determine whether frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU in the multi- GPU configuration and to send a message to initiate a data transfer mechanism when frequent cross tile memory accesses occur from the first GPU to the memory of the second GPU.

公开(公告)号：WO2020190369A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/014766

申请日：2020-01-23

Applicant: INTEL CORPORATION

Inventor： MATAM, Naveen ,  CHENEY, Lance ,  FINLEY, Eric ,  GEORGE, Varghese ,  JAHAGIRDAR, Sanjeev ,  KOKER, Altug ,  MASTRONARDE, Josh ,  RAJWANI, Iqbal ,  STRIRAMASSARMA, Lakshminarayanan ,  TESHOME, Melaku ,  VEMULAPALLI, Vikranth ,  XAVIER, Binoj

IPC: G06F13/40 ,  H01L25/11

Abstract: Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In one embodiment, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device.

公开(公告)号：WO2020190808A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/022846

申请日：2020-03-14

Applicant: INTEL CORPORATION

Inventor： RAY, Joydeep ,  JANUS, Scott ,  GEORGE, Varghese ,  MAIYURAN, Subramaniam ,  KOKER, Altug ,  APPU, Abhishek ,  SURTI, Prasoonkumar ,  RANGANATHAN, Vasanth ,  ANDREI, Valentin ,  GARG, Ashutosh ,  HAREL, Yoav ,  HUNTER, JR., Arthur ,  KIM, SungYe ,  MACPHERSON, Mike ,  OULD-AHMED-VALL, Elmoustapha ,  SADLER, William ,  STRIRAMASSARMA, Lakshminarayanan ,  VEMULAPALLI, Vikranth

IPC: G06F9/30 ,  G06F9/38

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.

公开(公告)号：WO2020190456A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/019532

申请日：2020-02-24

Applicant: INTEL CORPORATION

Inventor： GEORGE, Varghese ,  KOKER, Altug ,  ANANTARAMAN, Aravindh ,  MAIYURAN, Subramaniam ,  KIM, SungYe ,  ANDREI, Valentin ,  OULD-AHMED-VALL, Elmoustapha ,  RAY, Joydeep ,  APPU, Abhishek R. ,  GALOPPO VON BORRIES, Nicolas C. ,  SURTI, Prasoonkumar ,  MACPHERSON, Mike

IPC: G06F15/78 ,  G06F15/17

Abstract: Apparatuses including general-purpose graphics processing units having on chip dense memory for temporal buffering are disclosed. In one embodiment, a graphics multiprocessor includes a plurality of compute engines to perform first computations to generate a first set of data, cache for storing data, and a high density memory that is integrated on chip with the plurality of compute engines and the cache. The high density memory to receive the first set of data, to temporarily store the first set of data, and to provide the first set of data to the cache during a first time period that is prior to a second time period when the plurality of compute engines will use the first set of data for second computations.

公开(公告)号：WO2020190370A1

公开(公告)日：2020-09-24

申请号：PCT/US2020/014770

申请日：2020-01-23

Applicant: INTEL CORPORATION

Inventor： KOKER, Altug ,  CHENEY, Lance ,  FINLEY, Eric ,  GEORGE, Varghese ,  JAHAGIRDAR, Sanjeev ,  MASTRONARDE, Josh ,  MATAM, Naveen ,  RAJWANI, Iqbal ,  STRIRAMASSARMA, Lakshminarayanan ,  TESHOME, Melaku ,  VEMULAPALLI, Vikranth ,  XAVIER, Binoj

IPC: G06T1/20

Abstract: A disaggregated processor package can be configured to accept interchangeable chiplets. Interchangeability is enabled by specifying a standard physical interconnect for chiplets that can enable the chiplet to interface with a fabric or bridge interconnect. Chiplets from different IP designers can conform to the common interconnect, enabling such chiplets to be interchangeable during assembly. The fabric and bridge interconnects logic on the chiplet can then be configured to confirm with the actual interconnect layout of the onboard logic of the chiplet. Additionally, data from chiplets can be transmitted across an inter-chiplet fabric using encapsulation, such that the actual data being transferred is opaque to the fabric, further enable interchangeability of the individual chiplets. With such an interchangeable design, higher or lower density memory can be inserted into memory chiplet slots, while compute or graphics chiplets with a higher or lower core count can be inserted into logic chiplet slots.

公开(公告)号：WO2009014931A2

公开(公告)日：2009-01-29

申请号：PCT/US2008/069962

申请日：2008-07-14

Applicant: INTEL CORPORATION ,  JAHAGIRDAR, Sanjeev ,  GEORGE, Varghese ,  ALLAREY, Jose

Inventor： JAHAGIRDAR, Sanjeev ,  GEORGE, Varghese ,  ALLAREY, Jose

IPC: G06F1/32 ,  G06F15/16

CPC classification number: G06F1/3287 ,  G06F1/3203 ,  G06F1/3275 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/084 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/1048 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: A technique to retain cached information during a low power mode, according to at least one embodiment. In one embodiment, information stored in a processor's local cache is saved to a shared cache before the processor is placed into a low power mode, such that other processors may access information from the shared cache instead of causing the low power mode processor to return from the low power mode to service an access to its local cache.

Abstract translation: 根据至少一个实施例的在低功率模式期间保留缓存的信息的技术

。 在一个实施例中，在处理器被置于低功率模式之前，存储在处理器的本地高速缓存中的信息被保存到共享高速缓存，使得其他处理器可以访问来自共享高速缓存的信息而不是使低功率模式处理器从 低功耗模式来服务对本地缓存的访问。

公开(公告)号：WO2003003225A1

公开(公告)日：2003-01-09

申请号：PCT/US2002/019720

申请日：2002-06-20

Applicant: INTEL CORPORATION ,  GEORGE, Varghese ,  LANGENDORF, Brian

Inventor： GEORGE, Varghese ,  LANGENDORF, Brian

IPC: G06F13/10

CPC classification number: G06F13/105

Abstract: Virtual PCI bus appears from the perspective of a computer program to be a part of a physical hierarchical PCI bus structure residing behind a host-to-PCI bridge. Devices that are physically located on the host bus side of the host-to-PCI bridge may appear as virtual devices residing on the virtual PCI bus allowing the physical devices to participate in device independent initialization and system resource allocation generally available only to PCI compliant devices. Processor initiated host bus cycles targeted to the virtual PCI device may be intercepted and redirected to the physical device.

Abstract translation: 虚拟PCI总线从计算机程序的角度出现，成为位于主机到PCI桥后面的物理分层PCI总线结构的一部分。 物理上位于主机到PCI桥接器主机总线侧的设备可以显示为位于虚拟PCI总线上的虚拟设备，允许物理设备参与独立于设备的初始化和通常仅适用于PCI兼容设备的系统资源分配 。 针对虚拟PCI设备的处理器发起的主机总线周期可能会被拦截并重定向到物理设备。