公开(公告)号：US11824013B2

公开(公告)日：2023-11-21

申请号：US16541734

申请日：2019-08-15

Applicant: INTEL CORPORATION

Inventor： Lauren A. Link ,  Andrew J. Brown ,  Sheng C. Li ,  Sandeep B. Sane

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/14 ,  H01L23/15

CPC classification number: H01L23/562 ,  H01L23/145 ,  H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/351

Abstract: Techniques for mounting a semiconductor chip in a circuit board assembly includes using different buildup materials on opposite sides of a core to optimize stress in the first level interconnect structure (between the chip and core) and/or the second level interconnect structure (between the core and circuit board). The core can be, for example, ceramic, glass, or glass cloth-reinforced epoxy. In one example, the first side of the core has one or more layers of conductive material within a first buildup structure comprising a first buildup material. The second side of the substrate has one or more layers of conductive material within a second buildup structure comprising a second buildup material different from the first buildup material. In another example, an outermost layer of the second buildup structure is a ductile material that functions to decouple stress in the interconnect between the substrate and a circuit board.

公开(公告)号：US10811366B2

公开(公告)日：2020-10-20

申请号：US16249457

申请日：2019-01-16

Applicant: Intel Corporation

Inventor： Feras Eid ,  Robert L. Sankman ,  Sandeep B. Sane

IPC: H01L23/49 ,  H01L21/48 ,  H01L23/00 ,  H01L23/498

Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.

公开(公告)号：US10325860B2

公开(公告)日：2019-06-18

申请号：US15138480

申请日：2016-04-26

Applicant: Intel Corporation

Inventor： Feras Eid ,  Robert L. Sankman ,  Sandeep B. Sane

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: A microelectronic package may be fabricated with at least one compliant external bond pad having at least one integrated spring structure for mitigating the effects of warpage of the microelectronic package during attachment to an external substrate. An embodiment for the microelectronic package may include a microelectronic package substrate having a first surface and an opposing second surface, wherein the microelectronic package substrate includes a void defined therein that extends into the microelectronic package substrate from the second surface thereof, and a compliant bond pad suspended over the void, wherein the compliant bond pad includes a land portion and at least one spring portion, and wherein the at least one spring portion extends from the compliant bond pad land portion to an anchor structure on the microelectronic package substrate second surface.

公开(公告)号：US09659899B2

公开(公告)日：2017-05-23

申请号：US14796759

申请日：2015-07-10

Applicant: INTEL CORPORATION

Inventor： Sandeep B. Sane ,  Shankar Ganapathysubramanian ,  Jorge Sanchez ,  Leonel R. Arana ,  Eric J. Li ,  Nitin A. Deshpande ,  Jiraporn Seangatith ,  Poh Chieh Benny Poon

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC classification number: H01L24/32 ,  H01L23/562 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L24/89 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/3213 ,  H01L2224/32225 ,  H01L2224/32501 ,  H01L2224/32505 ,  H01L2224/73253 ,  H01L2224/81007 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/161 ,  H01L2924/16251 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2924/014

Abstract: Die warpage is controlled for the assembly of thin dies. In one example, a semiconductor die has a back side and a front side opposite the back side. The back side has a semiconductor substrate and the front side has components formed over the semiconductor substrate in front side layers. A backside layer is formed over the backside of the semiconductor die to resist warpage of the die when the die is heated and a plurality of contacts are formed on the front side of the die to attach to a substrate.

公开(公告)号：US11983135B2

公开(公告)日：2024-05-14

申请号：US17033593

申请日：2020-09-25

Applicant: Intel Corporation

Inventor： Dheeraj Subbareddy ,  Ankireddy Nalamalpu ,  Anshuman Thakur ,  Md Altaf Hossain ,  Mahesh Kumashikar ,  Kemal Aygün ,  Casey Thielen ,  Daniel Klowden ,  Sandeep B. Sane

IPC: G06F13/42 ,  G06F30/30 ,  G06F30/347

CPC classification number: G06F13/4221 ,  G06F13/4282 ,  G06F30/30 ,  G06F30/347 ,  G06F2213/0026

Abstract: Embodiments herein relate to systems, apparatuses, or processes for improving off-package edge bandwidth by overlapping electrical and optical serialization/deserialization (SERDES) interfaces on an edge of the package. In other implementations, off-package bandwidth for a particular edge of a package may use both an optical fanout and an electrical fanout on the same edge of the package. In embodiments, the optical fanout may use a top surface or side edge of a die and the electrical fanout may use the bottom side edge of the die. Other embodiments may be described and/or claimed.

公开(公告)号：US11557541B2

公开(公告)日：2023-01-17

申请号：US16235879

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Robert Sankman ,  Ravindranath V. Mahajan ,  Debendra Mallik ,  Ram S. Viswanath ,  Sandeep B. Sane ,  Sriram Srinivasan ,  Rajat Agarwal ,  Aravind Dasu ,  Scott Weber ,  Ravi Gutala

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

公开(公告)号：US20210287974A1

公开(公告)日：2021-09-16

申请号：US16328617

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Omkar G. Karhade ,  Nachiket R. Raravikar ,  Sandeep B. Sane

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a device disposed on first side of substrate and an array of conductive interconnect structures disposed on a second side of the first substrate. The conductive interconnect structures of the array may comprise a solder material, wherein the solder material comprises a low temperature alloying element concentration of less than about 5 percent. A second substrate is coupled to the array of conductive interconnect structures.

公开(公告)号：US20210280495A1

公开(公告)日：2021-09-09

申请号：US16328614

申请日：2016-09-29

Applicant: Intel Corporation

Inventor： Siddarth Kumar ,  Shubhada H. Sahasrabudhe ,  Sandeep B. Sane ,  Shalabh Tandon

IPC: H01L23/40 ,  H01L23/427 ,  H01L21/48

Abstract: Methods/structures of joining package structures are described. Those methods/structures may include a first side of a die disposed on a first side of a substrate, and a cooling structure on a second side of the die, wherein the cooling structure comprises a first section attached to the substrate, and a second section disposed on a second side of the die, wherein the first and second sections are separated by an opening in the cooling structure. The opening surrounds a portion of the second section, and at least one flexure beam structure connects the first and second sections.

公开(公告)号：US20170133350A1

公开(公告)日：2017-05-11

申请号：US14937022

申请日：2015-11-10

Applicant: Intel Corporation

Inventor： Shubhada H. Sahasrabudhe ,  Sandeep B. Sane ,  Siddarth Kumar ,  Shalabh Tandon

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/0657 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/17 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16055 ,  H01L2224/16057 ,  H01L2224/1607 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81193 ,  H01L2224/81365 ,  H01L2224/81815 ,  H01L2224/81951 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/1815

Abstract: Discussed generally herein are methods and devices for more reliable Package on Package (PoP) Through Mold Interconnects (TMIs). A device can include a first die package including a first conductive pad on or at least partially in the first die package, a dielectric mold material on the first die package, the mold material including a hole therethrough at least partially exposing the pad, a second die package including a second conductive pad on or at least partially in the second die package the second die package on the mold material such that the second conductive pad faces the first conductive pad through the hole, and a shape memory structure in the hole and forming a portion of a solder column electrical connection between the first die package and the second die package.