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    Integrated circuit with peek and poke protection circuitry for multi-tenant usage model
    1.
    发明授权
    Integrated circuit with peek and poke protection circuitry for multi-tenant usage model 有权

    公开(公告)号：US12265772B2

    公开(公告)日：2025-04-01

    申请号：US17850560

    申请日：2022-06-27

    Applicant: Intel Corporation

    Inventor： Scott Weber ,  Sean R. Atsatt ,  David Goldman

    IPC: G06F30/34 ,  G06F111/04

    Abstract: Methods and apparatus for extracting a setting of configuration bits to create an exclusion configuration for providing protection against peek and poke attacks in a multi-tenant usage model of a configurable device is provided. The device may host multiple parties that do not trust each other. Peek and poke attacks are orchestrated by tapping (peeking) and driving (poking) wires associated with other parties. Such attacks may be disabled by excluding the settings of configuration bits that would allow these attacks by other parties. This set of configuration bits that should be excluded for preventing all peek and poke attacks creates the exclusion configuration. Methods are described that disable a particular class of peek and/or poke attacks through the use of partial reconfiguration. Methods and apparatus are described to dynamically detect peek and/or poke attacks.

    SCALABLE RUNTIME VALIDATION FOR ON-DEVICE DESIGN RULE CHECKS
    3.
    发明申请
    SCALABLE RUNTIME VALIDATION FOR ON-DEVICE DESIGN RULE CHECKS 有权

    公开(公告)号：US20230089869A1

    公开(公告)日：2023-03-23

    申请号：US18070655

    申请日：2022-11-29

    Applicant: Intel Corporation

    Inventor： Furkan Turan ,  Patrick Koeberl ,  Alpa Trivedi ,  Steffen Schulz ,  Scott Weber

    IPC: G06F21/85 ,  G06F30/398 ,  G06N3/04 ,  H04L9/08 ,  G06F9/30 ,  G06F9/50 ,  G06F15/177 ,  G06F15/78 ,  H04L9/40 ,  G06F11/07 ,  G06F30/331 ,  G06F9/38 ,  G06F11/30

    Abstract: An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, multiplexers, and a validator. In one implementation, the validator is to: receive design rule information for the multiplexers, the design rule information referencing the contention set, wherein the contention set identifies a determined harmful bitstream configuration for each multiplexer instance of the multiplexers, and wherein the contention set comprises a mapping of contents of a user bitstream to configuration bits of the multiplexers; receive, at the validator of the apparatus, the user bitstream for programming the multiplexers of the apparatus; analyze, at the validator using the design rule information, the user bitstream against the contention set at a programming time of the apparatus; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.

    Three Dimensional Circuit Systems And Methods Having Memory Hierarchies
    5.
    发明申请
    Three Dimensional Circuit Systems And Methods Having Memory Hierarchies 有权

    公开(公告)号：US20220405005A1

    公开(公告)日：2022-12-22

    申请号：US17349592

    申请日：2021-06-16

    Applicant: Intel Corporation

    Inventor： Scott Weber ,  Jawad Khan ,  Ilya Ganusov ,  Martin Langhammer ,  Matthew Adiletta ,  Terence Magee ,  Albert Fazio ,  Richard Coulson ,  Ravi Gutala ,  Aravind Dasu ,  Mahesh Iyer

    IPC: G06F3/06

    Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

    SCALABLE RUNTIME VALIDATION FOR ON-DEVICE DESIGN RULE CHECKS
    6.
    发明申请
    SCALABLE RUNTIME VALIDATION FOR ON-DEVICE DESIGN RULE CHECKS 有权

    公开(公告)号：US20210110099A1

    公开(公告)日：2021-04-15

    申请号：US17132306

    申请日：2020-12-23

    Applicant: Intel Corporation

    Inventor： Furkan Turan ,  Patrick Koeberl ,  Alpa Trivedi ,  Steffen Schulz ,  Scott Weber

    IPC: G06F30/398

    Abstract: An apparatus to facilitate scalable runtime validation for on-device design rule checks is disclosed. The apparatus includes a memory to store a contention set, one or more multiplexors, and a validator communicably coupled to the memory. In one implementation, the validator is to: receive design rule information for the one or more multiplexers, the design rule information referencing the contention set; analyze, using the design rule information, a user bitstream against the contention set at a programming time of the apparatus, the user bitstream for programming the one or more multiplexors; and provide an error indication responsive to identifying a match between the user bitstream and the contention set.

    Voltage regulator circuit systems and methods
    7.
    发明授权
    Voltage regulator circuit systems and methods 有权

    公开(公告)号：US12253870B2

    公开(公告)日：2025-03-18

    申请号：US17352194

    申请日：2021-06-18

    Applicant: Intel Corporation

    Inventor： Archanna Srinivasan ,  Ravi Gutala ,  Scott Weber ,  Aravind Dasu ,  Mahesh Iyer ,  Eriko Nurvitadhi

    IPC: G05F1/575 ,  G05F1/577 ,  H01L25/065 ,  H03K19/00

    Abstract: A circuit system includes a first voltage regulator circuit that generates a first supply voltage for an integrated circuit die based on a first control signal. The first voltage regulator circuit generates a first feedback signal based on the first supply voltage. The circuit system also includes a second voltage regulator circuit that generates a second supply voltage for an integrated circuit die based on a second control signal. The second voltage regulator circuit generates a second feedback signal based on the second supply voltage. The circuit system also includes a third voltage regulator circuit that generates the first control signal based on the first feedback signal and the second control signal based on the second feedback signal. The circuit system may include fully integrated, on-board, and on-package voltage regulator circuits.

    Three Dimensional Programmable Logic Circuit Systems And Methods
    10.
    发明申请
    Three Dimensional Programmable Logic Circuit Systems And Methods 有权

    公开(公告)号：US20210313988A1

    公开(公告)日：2021-10-07

    申请号：US17354473

    申请日：2021-06-22

    Applicant: Intel Corporation

    Inventor： Scott Weber ,  Aravind Dasu ,  Ravi Gutala ,  Mahesh Iyer ,  Eriko Nurvitadhi ,  Archanna Srinivasan ,  Sean Atsatt ,  James Ball

    IPC: H03K19/17736 ,  H03K19/1776 ,  H03K19/17768 ,  H01L25/18

    Abstract: A three dimensional circuit system includes first and second integrated circuit (IC) dies. The first IC die includes programmable logic circuits arranged in sectors and first programmable interconnection circuits having first router circuits. The second IC die includes non-programmable circuits arranged in regions and second programmable interconnection circuits having second router circuits. Each of the regions in the second IC die is vertically aligned with at least one of the sectors in the first IC die. Each of the second router circuits is coupled to one of the first router circuits through a vertical die-to-die connection. The first and second programmable interconnection circuits are programmable to route signals between the programmable logic circuits and the non-programmable circuits through the first and second router circuits. The circuit system may include additional IC dies. The first and second IC dies and any additional IC dies are coupled in a vertically stacked configuration.

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