公开(公告)号：US11557541B2

公开(公告)日：2023-01-17

申请号：US16235879

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Md Altaf Hossain ,  Ankireddy Nalamalpu ,  Dheeraj Subbareddy ,  Robert Sankman ,  Ravindranath V. Mahajan ,  Debendra Mallik ,  Ram S. Viswanath ,  Sandeep B. Sane ,  Sriram Srinivasan ,  Rajat Agarwal ,  Aravind Dasu ,  Scott Weber ,  Ravi Gutala

IPC: H01L23/538 ,  H01L25/18 ,  H01L23/00 ,  H01L23/48

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.

公开(公告)号：US20220405005A1

公开(公告)日：2022-12-22

申请号：US17349592

申请日：2021-06-16

Applicant: Intel Corporation

Inventor： Scott Weber ,  Jawad Khan ,  Ilya Ganusov ,  Martin Langhammer ,  Matthew Adiletta ,  Terence Magee ,  Albert Fazio ,  Richard Coulson ,  Ravi Gutala ,  Aravind Dasu ,  Mahesh Iyer

IPC: G06F3/06

Abstract: A three dimensional circuit system includes a first integrated circuit die having a core logic region that has first memory circuits and logic circuits. The three dimensional circuit system includes a second integrated circuit die that has second memory circuits. The first and second integrated circuit dies are coupled together in a vertically stacked configuration. The three dimensional circuit system includes third memory circuits coupled to the first integrated circuit die. The third memory circuits reside in a plane of the first integrated circuit die. The logic circuits are coupled to access the first, second, and third memory circuits and data can move between the first, second, and third memories. The third memory circuits have a larger memory capacity and a smaller memory access bandwidth than the second memory circuits. The second memory circuits have a larger memory capacity and a smaller memory access bandwidth than the first memory circuits.

公开(公告)号：US11237757B2

公开(公告)日：2022-02-01

申请号：US15645951

申请日：2017-07-10

Applicant: Intel Corporation

Inventor： Ravi Gutala ,  Aravind Dasu

IPC: G06F3/06 ,  H03K19/00 ,  G06F15/76 ,  G06F30/00

Abstract: An integrated circuit package includes a memory integrated circuit die and a coprocessor integrated circuit die that is coupled to the memory integrated circuit die. The coprocessor integrated circuit die has a logic sector that is configured to accelerate a function for a host processor. The logic sector generates an intermediate result of a computation performed as part of the function. The intermediate result is transmitted to and stored in the memory integrated circuit die.

公开(公告)号：US10778414B2

公开(公告)日：2020-09-15

申请号：US16372297

申请日：2019-04-01

Applicant: Intel Corporation

Inventor： Peter John McElheny ,  Aravind Dasu

IPC: G11C5/02 ,  H04L9/06 ,  H01L23/498 ,  H01L23/367 ,  H01L25/065 ,  H01L25/18 ,  H03K19/177 ,  H03K19/1776 ,  H01L23/00 ,  H01L23/36

Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.

公开(公告)号：US20190229888A1

公开(公告)日：2019-07-25

申请号：US16372297

申请日：2019-04-01

Applicant: Intel Corporation

Inventor： Peter John McElheny ,  Aravind Dasu

IPC: H04L9/06 ,  H01L25/065 ,  H01L23/498 ,  H01L25/18 ,  H03K19/177 ,  H01L23/367

Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.

公开(公告)号：US12046578B2

公开(公告)日：2024-07-23

申请号：US16914164

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Naveed Zaman ,  Aravind Dasu ,  Sreedhar Ravipalli ,  Rakesh Cheerla ,  Martin Horne

IPC: H01L25/065 ,  H04L9/40 ,  H04L47/10 ,  H04L49/90

CPC classification number: H01L25/0657 ,  H04L47/10 ,  H04L49/90 ,  H04L63/1458

Abstract: A smart network interface controller (NIC) implemented using a stacked die configuration is provided. The NIC may include user-customizable networking circuits formed in a top programmable die and primitive network function blocks formed in a bottom application-specific integrated circuit (ASIC) die. The top programmable die may provide a flexible packet processing pipeline to facilitate efficient control and data communication between the user-customizable networking circuits and the primitive network function blocks. The bottom ASIC die may also include an array of memory blocks operable as lookup tables and intermediate buffers for other network processing circuitry in the NIC. A NIC configured in this way provides both performance, power, and area benefits and superior customer configurability.

公开(公告)号：US10964624B2

公开(公告)日：2021-03-30

申请号：US15416589

申请日：2017-01-26

Applicant: Intel Corporation

Inventor： Ravi Gutala ,  Aravind Dasu

IPC: H01L23/473 ,  H01L25/065 ,  G11C7/04 ,  H05K7/20 ,  H01L23/00

Abstract: A method is provided for removing heat from an integrated circuit package. Fluid coolant is provided from a fluid inlet of a fluid routing device through channels in the fluid routing device to absorb heat generated by first and second integrated circuit dies in the integrated circuit package. The fluid routing device is mounted on a surface of each of the first and second integrated circuit dies. The fluid coolant is provided from the channels to a fluid outlet of the fluid routing device. A flow of the fluid coolant through the fluid routing device is adjusted to reduce a temperature of the first integrated circuit die in response to an increase in a workload of the first integrated circuit die.

公开(公告)号：US20200374102A1

公开(公告)日：2020-11-26

申请号：US16992946

申请日：2020-08-13

Applicant: Intel Corporation

Inventor： Peter John McElheny ,  Aravind Dasu

IPC: H04L9/06 ,  H01L23/498 ,  H01L23/367 ,  H01L25/065 ,  H01L25/18 ,  H03K19/177 ,  H03K19/1776

Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.

公开(公告)号：US20180176006A1

公开(公告)日：2018-06-21

申请号：US15381981

申请日：2016-12-16

Applicant: Intel Corporation

Inventor： Peter John McElheny ,  Aravind Dasu

IPC: H04L9/06 ,  H01L23/498 ,  H01L23/367 ,  H01L25/065

CPC classification number: H04L9/065 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06589 ,  H01L2924/1431 ,  H01L2924/1437 ,  H01L2924/1443 ,  H03K19/177 ,  H03K19/1776

Abstract: A system may include a host processor, an interposer having memory elements, a coprocessor mounted on the interposer for accelerating tasks received from the host processor, and an auxiliary chip. The coprocessor, interposer, and auxiliary chip may be part of an integrated circuit package. The memory elements on the interposer may convey configuration bit streams to one or more logic sectors in programmable circuitry of the coprocessor. The interposer may be connected to a package substrate of the integrated circuit package using through-silicon vias, such that an active surface of the interposer faces an active surface of the coprocessor. Each logic sector may include one or more data registers that are loaded with configuration data from the memory elements. In some instances, the auxiliary chip may include a secondary memory for storing additional configuration bit streams for configuring the logic sectors of the coprocessor.

公开(公告)号：US12255648B2

公开(公告)日：2025-03-18

申请号：US17350577

申请日：2021-06-17

Applicant: Intel Corporation

Inventor： Archanna Srinivasan ,  Ravi Gutala ,  Scott Weber ,  Aravind Dasu ,  Mahesh Iyer ,  Eriko Nurvitadhi

IPC: H03K19/17788 ,  H03K19/17728 ,  H03K19/17792

Abstract: A circuit system includes a first integrated circuit die having a first group of circuits configured to perform a first set of operations. The circuit system also includes a second integrated circuit die having a second group of circuits configured to start performing a second set of operations with a delay after the first group of circuits starts performing the first set of operations to reduce power supply voltage droop. The operations performed by the first and second groups of circuits can be interleaved with a fixed or a variable delay. Logic circuits can be partitioned into the first and the second groups of circuits based on predicted switching activity of the logic circuits. Decoupling capacitors in integrated circuit dies can be coupled together to reduce droop in a supply voltage during a high current event.