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    Systolic array of arbitrary physical and logical depth
    15.
    发明授权
    Systolic array of arbitrary physical and logical depth 有权

    公开(公告)号：US12174783B2

    公开(公告)日：2024-12-24

    申请号：US17304678

    申请日：2021-06-24

    Applicant: Intel Corporation

    Inventor： Jorge Parra ,  Wei-yu Chen ,  Kaiyu Chen ,  Varghese George ,  Junjie Gu ,  Chandra Gurram ,  Guei-Yuan Lueh ,  Stephen Junkins ,  Subramaniam Maiyuran ,  Supratim Pal

    IPC: G06F15/80 ,  G06F9/50 ,  G06F9/54 ,  G06T1/20

    Abstract: A processing apparatus includes a processing resource including a general-purpose parallel processing engine and a matrix accelerator. The matrix accelerator includes first circuitry to receive a command to perform operations associated with an instruction, second circuitry to configure the matrix accelerator according to a physical depth of a systolic array within the matrix accelerator and a logical depth associated with the instruction, third circuitry to read operands for the instruction from a register file associated with the systolic array, fourth circuitry to perform operations for the instruction via one or more passes through one or more physical pipeline stages of the systolic array based on a configuration performed by the second circuitry, and fifth circuitry to write output of the operations to the register file associated with the systolic array.

    SHARED LOCAL REGISTERS FOR THREAD TEAM PROCESSING
    18.
    发明公开
    SHARED LOCAL REGISTERS FOR THREAD TEAM PROCESSING 审中-公开

    公开(公告)号：US20240112295A1

    公开(公告)日：2024-04-04

    申请号：US17958216

    申请日：2022-09-30

    Applicant: Intel Corporation

    Inventor： Biju George ,  Fangwen Fu ,  Supratim Pal ,  Jorge Parra ,  Chunhui Mei ,  Maxim Kazakov ,  Joydeep Ray

    IPC: G06T1/20 ,  G06F9/30 ,  G06F9/38

    CPC classification number: G06T1/20 ,  G06F9/30098 ,  G06F9/3836

    Abstract: Shared local registers for thread team processing is described. An example of an apparatus includes one or more processors including a graphic processor having multiple processing resources; and memory for storage of data, the graphics processor to allocate a first thread team to a first processing resource, the first thread team including hardware threads to be executed solely by the first processing resource; allocate a shared local register (SLR) space that may be directly reference in the ISA instructions to the first processing resource, the SLR space being accessible to the threads of the thread team and being inaccessible to threads outside of the thread team; and allocate individual register spaces to the thread team, each of the individual register spaces being accessible to a respective thread of the thread team.

    SYNCHRONIZATION UTILIZING LOCAL TEAM BARRIERS FOR THREAD TEAM PROCESSING
    19.
    发明公开
    SYNCHRONIZATION UTILIZING LOCAL TEAM BARRIERS FOR THREAD TEAM PROCESSING 审中-公开

    公开(公告)号：US20240111609A1

    公开(公告)日：2024-04-04

    申请号：US17958213

    申请日：2022-09-30

    Applicant: Intel Corporation

    Inventor： Biju George ,  Supratim Pal ,  James Valerio ,  Vasanth Ranganathan ,  Fangwen Fu ,  Chunhui Mei

    IPC: G06F9/52 ,  G06F9/30

    CPC classification number: G06F9/522 ,  G06F9/30098

    Abstract: Low-latency synchronization utilizing local team barriers for thread team processing is described. An example of an apparatus includes one or more processors including a graphics processor, the graphics processor including a plurality of processing resources; and memory for storage of data including data for graphics processing, wherein the graphics processor is to receive a request for establishment of a local team barrier for a thread team, the thread team being allocated to a first processing resource, the thread team including multiple threads; determine requirements and designated threads for the local team barrier; and establish the local team barrier in a local register of the first processing resource based at least in part on the requirements and designated threads for the local barrier.

    GATHERING PAYLOAD FROM ARBITRARY REGISTERS FOR SEND MESSAGES IN A GRAPHICS ENVIRONMENT
    20.
    发明申请
    GATHERING PAYLOAD FROM ARBITRARY REGISTERS FOR SEND MESSAGES IN A GRAPHICS ENVIRONMENT 有权

    公开(公告)号：US20230088743A1

    公开(公告)日：2023-03-23

    申请号：US17481448

    申请日：2021-09-22

    Applicant: Intel Corporation

    Inventor： Supratim Pal ,  Chandra Gurram ,  Fan-Yin Tzeng ,  Subramaniam Maiyuran ,  Guei-Yuan Lueh ,  Timothy R. Bauer ,  Vikranth Vemulapalli ,  Wei-Yu Chen

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/02 ,  G06T1/20

    Abstract: An apparatus to facilitate gathering payload from arbitrary registers for send messages in a graphics environment is disclosed. The apparatus includes processing resources comprising execution circuitry to receive a send gather message instruction identifying a number of registers to access for a send message and identifying IDs of a plurality of individual registers corresponding to the number of registers; decode a first phase of the send gather message instruction; based on decoding the first phase, cause a second phase of the send gather message instruction to bypass an instruction decode stage; and dispatch the first phase subsequently followed by dispatch of the second phase to a send pipeline. The apparatus can also perform an immediate move of the IDs of the plurality of individual registers to an architectural register of the execution circuitry and include a pointer to the architectural register in the send gather message instruction.

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