公开(公告)号：US20240005136A1

公开(公告)日：2024-01-04

申请号：US18351124

申请日：2023-07-12

Applicant: Intel Corporation

Inventor： Kamal Sinha ,  Balaji Vembu ,  Eriko Nurvitadhi ,  Nicolas C. Galoppo Von Borries ,  Rajkishore Barik ,  Tsung-Han Lin ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Anbang Yao ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Farshad Akhbari ,  Narayan Srinivasa ,  Feng Chen ,  Dukhwan Kim ,  Nadathur Rajagopalan Satish ,  John C. Weast ,  Mike B. MacPherson ,  Linda L. Hurd ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G06T1/20 ,  G06F9/30 ,  G06T15/00 ,  G06F15/78 ,  G06F15/76 ,  G06F1/3287 ,  G06F1/3293 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045

CPC classification number: G06N3/063 ,  G06N3/08 ,  G06N3/04 ,  G06T1/20 ,  G06F9/30014 ,  G06T15/005 ,  G06F15/78 ,  G06F15/76 ,  G06F9/30036 ,  G06F1/3287 ,  G06F1/3293 ,  G06N3/084 ,  G06N3/044 ,  G06N3/045 ,  G06T1/60

Abstract: In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

公开(公告)号：US20230351543A1

公开(公告)日：2023-11-02

申请号：US18310688

申请日：2023-05-02

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Scott Janus ,  Varghese George ,  Subramaniam Maiyuran ,  Altug Koker ,  Abhishek Appu ,  Prasoonkumar Surti ,  Vasanth Ranganathan ,  Valentin Andrei ,  Ashutosh Garg ,  Yoav Harel ,  Arthur Hunter, JR. ,  SungYe Kim ,  Mike Macpherson ,  Elmoustapha Ould-Ahmed-Vall ,  William Sadler ,  Lakshminarayanan Striramassarma ,  Vikranth Vemulapalli

IPC: G06N3/084 ,  G06F15/80 ,  G06F17/16 ,  G06N3/048 ,  G06T1/20 ,  G06F9/50 ,  G06F12/0806 ,  G06F7/544 ,  G06N3/08

CPC classification number: G06T1/20 ,  G06F7/5443 ,  G06F9/5027 ,  G06F12/0806 ,  G06F15/8046 ,  G06F17/16 ,  G06N3/048 ,  G06N3/08 ,  G06N3/084

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements output by a processing resource and generate metadata to indicate a location of the zero value elements within the plurality of data elements.

公开(公告)号：US11726826B2

公开(公告)日：2023-08-15

申请号：US17339184

申请日：2021-06-04

Applicant: Intel Corporation

Inventor： James Valerio ,  Vasanth Ranganathan ,  Joydeep Ray ,  Rahul A. Kulkarni ,  Abhishek R. Appu ,  Jeffery S. Boles ,  Hema C. Nalluri

IPC: G06F9/50 ,  G06F9/48 ,  G06T1/20 ,  G06F9/38

CPC classification number: G06F9/5038 ,  G06F9/3822 ,  G06F9/3867 ,  G06F9/4881 ,  G06F9/5066 ,  G06T1/20

Abstract: Examples are described here that can be used to allocate commands from multiple sources to performance by one or more segments of a processing device. For example, a processing device can be segmented into multiple portions and each portion is allocated to process commands from a particular source. In the event a single source provides commands, the entire processing device (all segments) can be allocated to process commands from the single source. When a second source provides commands, some segments can be allocated to perform commands from the first source and other segments can be allocated to perform commands from the second source. Accordingly, commands from multiple applications can be executed by a processing unit at the same time.

公开(公告)号：US11676239B2

公开(公告)日：2023-06-13

申请号：US17303654

申请日：2021-06-03

Applicant: Intel Corporation

Inventor： Joydeep Ray ,  Scott Janus ,  Varghese George ,  Subramaniam Maiyuran ,  Altug Koker ,  Abhishek Appu ,  Prasoonkumar Surti ,  Vasanth Ranganathan ,  Andrei Valentin ,  Ashutosh Garg ,  Yoav Harel ,  Arthur Hunter, Jr. ,  SungYe Kim ,  Mike Macpherson ,  Elmoustapha Ould-Ahmed-Vall ,  William Sadler ,  Lakshminarayanan Striramassarma ,  Vikranth Vemulapalli

IPC: G06T1/20 ,  G06F9/50 ,  G06F12/0806 ,  G06F15/80 ,  G06F17/16 ,  G06F7/544 ,  G06N3/04 ,  G06N3/08 ,  G06N3/084 ,  G06N3/048

CPC classification number: G06T1/20 ,  G06F7/5443 ,  G06F9/5027 ,  G06F12/0806 ,  G06F15/8046 ,  G06F17/16 ,  G06N3/048 ,  G06N3/08 ,  G06N3/084

Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.

公开(公告)号：US11670044B2

公开(公告)日：2023-06-06

申请号：US17723328

申请日：2022-04-18

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Subhajit Dasgupta ,  Srivallaba Mysore ,  Michael J. Norris ,  Vasanth Ranganathan ,  Joydeep Ray

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

CPC classification number: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T2210/52

Abstract: One embodiment provides for a graphics processing unit comprising a processing cluster to perform coarse pixel shading and output shaded coarse pixels for processing by a pixel processing pipeline and a render cache to store coarse pixel data for input to or output from a pixel processing pipeline.

公开(公告)号：US11586548B2

公开(公告)日：2023-02-21

申请号：US17191473

申请日：2021-03-03

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  David Puffer ,  Prasoonkumar Surti ,  Lakshminarayanan Striramassarma ,  Vasanth Ranganathan ,  Kiran C. Veernapu ,  Balaji Vembu ,  Pattabhiraman K

IPC: G06F12/0877 ,  G06F12/0802 ,  G06F12/0855 ,  G06F12/0806 ,  G06F12/0846 ,  G06F12/0868 ,  G06T1/60 ,  G06F12/126 ,  G06F12/0893

Abstract: In an example, an apparatus comprises a plurality of execution units, and a cache memory communicatively coupled to the plurality of execution units, wherein the cache memory is structured into a plurality of sectors, wherein each sector in the plurality of sectors comprises at least two cache lines. Other embodiments are also disclosed and claimed.

公开(公告)号：US11520723B2

公开(公告)日：2022-12-06

申请号：US17367169

申请日：2021-07-02

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Kiran C. Veernapu ,  Balaji Vembu ,  Vasanth Ranganathan ,  Prasoonkumar Surti

IPC: G06F13/40 ,  G06F9/54 ,  G06F13/42 ,  G06T1/60 ,  G06F12/084 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0831

Abstract: Methods and apparatus relating to techniques for avoiding cache lookup for cold cache. In an example, an apparatus comprises logic, at least partially comprising hardware logic, to monitor a thread switching overhead parameter for an application executing in a processing system and in response to a determination that the thread switching overhead parameter exceeds a threshold, to activate a thread management algorithm to reduce thread switching in the processing system. Other embodiments are also disclosed and claimed.

公开(公告)号：US11360767B2

公开(公告)日：2022-06-14

申请号：US17305355

申请日：2021-07-06

Applicant: Intel Corporation

Inventor： Himanshu Kaul ,  Mark A. Anders ,  Sanu K. Mathew ,  Anbang Yao ,  Joydeep Ray ,  Ping T. Tang ,  Michael S. Strickland ,  Xiaoming Chen ,  Tatiana Shpeisman ,  Abhishek R. Appu ,  Altug Koker ,  Kamal Sinha ,  Balaji Vembu ,  Nicolas C. Galoppo Von Borries ,  Eriko Nurvitadhi ,  Rajkishore Barik ,  Tsung-Han Lin ,  Vasanth Ranganathan ,  Sanjeev Jahagirdar

IPC: G06F9/30 ,  G09G5/393 ,  G06F9/38 ,  G06F7/483 ,  G06F7/544 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08 ,  G06T15/00 ,  G06N20/00 ,  G06F17/16

Abstract: A processing apparatus is provided comprising a multiprocessor having a multithreaded architecture. The multiprocessor can execute at least one single instruction to perform parallel mixed precision matrix operations. In one embodiment the apparatus includes a memory interface and an array of multiprocessors coupled to the memory interface. At least one multiprocessor in the array of multiprocessors is configured to execute a fused multiply-add instruction in parallel across multiple threads.

公开(公告)号：US11353868B2

公开(公告)日：2022-06-07

申请号：US15495112

申请日：2017-04-24

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan

IPC: G06N3/08 ,  G05D1/00 ,  G06F9/52 ,  G06N3/063 ,  G06N3/04 ,  G06F9/46 ,  G06T1/20

Abstract: One or more examples include an apparatus having a hardware barrier logic to detect thread groups relating to machine learning operations and facilitate barrier synchronization of the thread groups across multiple dies representing multiple processors, such that data processing using the threads groups across the multiple processors is synchronized and stall-free.

公开(公告)号：US11315311B2

公开(公告)日：2022-04-26

申请号：US16922094

申请日：2020-07-07

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Subhajit Dasgupta ,  Srivallaba Mysore ,  Michael J. Norris ,  Vasanth Ranganathan ,  Joydeep Ray

IPC: G06T15/80 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: One embodiment provides for a graphics processing unit comprising a processing cluster to perform coarse pixel shading and output shaded coarse pixels for processing by a pixel processing pipeline and a render cache to store coarse pixel data for input to or output from pixel processing pipeline.