公开(公告)号：DE112013006064T5

公开(公告)日：2015-08-27

申请号：DE112013006064

申请日：2013-12-17

Applicant: INTEVAC INC

Inventor： ADIBI BABAK ,  HIESLMAIR HENRY

IPC: H01L31/00

Abstract: Eine photovoltaische Zelle mit einer abgestuft dotierten Region, beispielsweise einem abgestuften Emitter, und ein Verfahren zur Herstellung von photovoltaischen Zellen mit abgestuft dotierten Regionen, beispielsweise abgestuften Emittern, sind offenbart. Die Dotierung wird über die Oberfläche eingestellt, um den Widerstands-Leistungsverlust (I2R) zu minimieren. Die abgestuften Emitter liefern eine abgestufte Änderung in dem Schichtwiderstand über dem gesamten Abstand zwischen den Linien. Das abgestufte Emitterprofil kann einen niedrigeren Schichtwiderstand nahe bei den Metalllinien und einen höheren Schichtwiderstand weiter weg von den Metalllinienkanten aufweisen. Der Schichtwiderstand wird so abgestuft, dass der Schichtwiderstand geringer ist, wo die I2R-Leistungsverluste aufgrund von Stromstau am höchsten sind. Ein Vorteil des abgestuften Emitters gegenüber selektiven Emittern ist ein verbesserter Wirkungsgrad. Ein zusätzlicher Vorteil der abgestuften Emitter gegenüber den selektiven Emittern ist eine verbesserte Leichtigkeit bei der Ausrichtung der Metallisierung gegenüber den Regionen mit niedrigem Schichtwiderstand.

公开(公告)号：WO2014100506A4

公开(公告)日：2014-08-14

申请号：PCT/US2013076741

申请日：2013-12-19

Applicant: INTEVAC INC ,  PRABHAKAR VINAY ,  ADIBI BABAK

Inventor： PRABHAKAR VINAY ,  ADIBI BABAK

IPC: G21K5/04 ,  G21K5/10 ,  H01L21/265 ,  H01L21/266 ,  H01L21/425 ,  H01L21/426

CPC classification number: H01L31/0516 ,  H01J37/32412 ,  H01J37/32422 ,  H01J37/32623 ,  H01J2237/20 ,  H01J2237/3365 ,  H01L21/266 ,  H01L21/426 ,  H01L31/0682 ,  H01L31/1804 ,  H01L31/188 ,  Y02E10/50 ,  Y02E10/547 ,  Y02P70/521

Abstract: A grid for minimizing effects of ion divergence in plasma ion implant. The plasma grid is made of a flat plate having a plurality of holes, wherein the holes are arranged in a plurality of rows and a plurality of columns thereby forming beamlets of ions that diverge in one direction. A mask is used to form the implanted shapes on the wafer, wherein the holes in the mask are oriented orthogonally to the direction of beamlet divergence.

Abstract translation: 用于最小化等离子体离子注入中离子发散效应的网格。 等离子体栅格由具有多个孔的平板制成，其中孔布置成多行和多列，从而形成沿一个方向发散的离子小射束。 使用掩模在晶片上形成注入形状，其中掩模中的孔与小射束发散的方向正交取向。

公开(公告)号：WO2013070978A3

公开(公告)日：2013-08-08

申请号：PCT/US2012064241

申请日：2012-11-08

Applicant: INTEVAC INC ,  PEDERSON TERRY ,  HIESLMAIR HENRY ,  CHUN MOON ,  PRABHAKAR VINAY ,  ADIBI BABAK ,  BLUCK TERRY

Inventor： PEDERSON TERRY ,  HIESLMAIR HENRY ,  CHUN MOON ,  PRABHAKAR VINAY ,  ADIBI BABAK ,  BLUCK TERRY

IPC: H01L21/677 ,  H01L21/687

CPC classification number: H01L21/6833 ,  H01L21/26506 ,  H01L21/67745 ,  H01L21/6776 ,  H01L21/681 ,  H01L21/6831 ,  H01L31/1876 ,  H02N13/00 ,  Y02E10/50 ,  Y02P70/521

Abstract: A system for processing substrates has a vacuum enclosure and a processing chamber situated to process wafers in a processing zone inside the vacuum enclosure. Two rail assemblies are provided, one on each side of the processing zone. Two chuck arrays ride, each on one of the rail assemblies, such that each is cantilevered on one rail assemblies and support a plurality of chucks. The rail assemblies are coupled to an elevation mechanism that places the rails in upper position for processing and at lower position for returning the chuck assemblies for loading new wafers. A pickup head assembly loads wafers from a conveyor onto the chuck assemblies. The pickup head has plurality of electrostatic chucks that pick up the wafers from the front side of the wafers.

Abstract translation: 一种用于处理基板的系统具有真空外壳和处理室，该处理室被设置用于在真空外壳内部的处理区中处理晶片。 提供两个导轨组件，处理区域的每一侧各有一个导轨组件。 两个卡盘阵列分别在一个导轨组件上骑行，使得每个卡盘阵列悬臂在一个导轨组件上并支撑多个卡盘。 所述导轨组件联接到升降机构，所述升降机构将所述导轨放置在用于处理的上部位置中，并且在降低位置用于使所述卡盘组件返回以加载新的晶片。 拾取头组件将来自传送器的晶片加载到卡盘组件上。 拾取头具有多个从晶片的正面拾取晶片的静电夹盘。

公开(公告)号：MY192712A

公开(公告)日：2022-09-05

申请号：MYPI2018702478

申请日：2017-01-18

Applicant: INTEVAC INC

Inventor： BLUCK TERRY ,  ADIBI BABAK ,  PRABHAKAR VINAY ,  RUNSTADLER JR WILLIAM EUGENE

IPC: H01L21/68 ,  H01L21/66 ,  H01L21/67 ,  H01L21/683 ,  H01L21/687

Abstract: A chuck (300, 400, 900) for wafer processing that counters the deleterious effects of thermal expansion of the wafer (308, 408, 608). Also, a combination of chuck (300, 400, 900) and shadow mask arrangement that maintains relative alignment between openings in the mask and the wafer in spite of thermal expansion of the wafer (308, 408, 608). A method for fabricating a solar cell by ion implant, while maintaining relative alignment of the implanted features during thermal expansion of the wafer.

公开(公告)号：MY178951A

公开(公告)日：2020-10-23

申请号：MYPI2015001591

申请日：2013-12-19

Applicant: INTEVAC INC

Inventor： PRABHAKAR VINAY ,  ADIBI BABAK

Abstract: A grid for minimizing effects of ion divergence in plasma ion implant. The plasma grid is made of a flat plate having a plurality of holes, wherein the holes are arranged in a plurality of rows and a plurality of columns thereby forming beam lets (115, 615) of ions that diverge in one direction. A mask (125, 625, 725) is used to form the implanted shapes on the wafer (120, 620), wherein the holes in the mask are oriented orthogonally to the direction of beamlet divergence.

公开(公告)号：SG10201500916VA

公开(公告)日：2015-04-29

申请号：SG10201500916V

申请日：2011-02-09

Applicant: INTEVAC INC

Inventor： CHUN MOON ,  ADIBI BABAK

Abstract: An adjustable shadow mask implantation system comprising: an ion source configured to provides ions; and an shadow mask assembly configured to selectively allow ions from the ion source to pass there through to a substrate where they are implanted, wherein the shadow mask assembly is configured to adjust between a first position and a second position, wherein the shadow mask assembly enables ion implantation of multiple substantially parallel lines absent any lines with an intersecting orientation with respect to the multiple substantially parallel lines when set in the first position, and wherein the shadow mask assembly enables ion implantation of multiple substantially parallel lines and a line with an intersecting orientation with respect to the multiple substantially parallel lines when set in the second position.

公开(公告)号：SG190332A1

公开(公告)日：2013-06-28

申请号：SG2013038468

申请日：2011-11-17

Applicant: INTEVAC INC

Inventor： CHUN MOON ,  ADIBI BABAK

Abstract: An apparatus and methods for ion implantation of solar cells. The disclosure provide enhanced throughput and recued or elimination of defects after SPER anneal step. The substrate is continually implanted using continuous high dose-rate implantation, leading to efficient defect accumulation, i.e., amorphization, while suppressing dynamic self-annealing.

公开(公告)号：SG176547A1

公开(公告)日：2012-01-30

申请号：SG2011073079

申请日：2010-06-23

Applicant: INTEVAC INC

Inventor： ADIBI BABAK ,  CHUN MOON

Abstract: A method of ion implantation comprising: providing a plasma within a plasma region of a chamber; positively biasing a first grid plate, wherein the first grid plate comprises a plurality of apertures; negatively biasing a second grid plate, wherein the second grid plate comprises a plurality of apertures; flowing ions from the plasma in the plasma region through the apertures in the positively-biased first grid plate; flowing at least a portion of the ions that flowed through the apertures in the positively-biased first grid plate through the apertures in the negatively-biased second grid plate; and implanting a substrate with at least a portion of the ions that flowed through the apertures in the negatively-biased second grid plate.

公开(公告)号：EP2641266A4

公开(公告)日：2014-08-27

申请号：EP11841747

申请日：2011-11-17

Applicant: INTEVAC INC

Inventor： CHUN MOON ,  ADIBI BABAK

IPC: H01L21/20 ,  H01L21/223 ,  H01L21/324 ,  H01L31/18

CPC classification number: H01L31/1864 ,  H01L21/2236 ,  H01L21/324 ,  H01L31/068 ,  H01L31/1804 ,  H01L31/1872 ,  Y02E10/547 ,  Y02P70/521

公开(公告)号：EP2409331A4

公开(公告)日：2017-06-28

申请号：EP10754209

申请日：2010-03-19

Applicant: INTEVAC INC

Inventor： ADIBI BABAK ,  MURRER EDWARD ,  HIESLMAIR HENRY

IPC: H01L31/068 ,  H01L31/0224 ,  H01L31/18

CPC classification number: H01L31/022425 ,  H01L21/26513 ,  H01L31/022433 ,  H01L31/022441 ,  H01L31/068 ,  H01L31/0682 ,  H01L31/1804 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of fabricating a solar cell comprising: providing a semiconducting wafer having a front surface, a back surface, and a background doped region; performing a set of ion implantations of dopant into the semiconducting wafer to form a back alternatingly-doped region extending from the back surface of the semiconducting wafer to a location between the back surface and the front surface, wherein the back doped region comprises laterally alternating first back doped regions and second back doped regions, and wherein the first back doped regions comprise a different charge type than the second back doped regions and the background doped region; and disposing a back metal contact layer onto the back surface of the semiconducting wafer, wherein the back metal contact layer is aligned over the first and second back doped regions and is configured to conduct electrical charge from the first and second back doped regions.

Abstract translation: 一种制造太阳能电池的方法，包括：提供具有前表面，后表面和背景掺杂区的半导体晶片; 向所述半导体晶片中执行一组离子注入掺杂剂以形成从所述半导体晶片的所述后表面延伸到所述后表面与所述前表面之间的位置的后交替掺杂区，其中所述后掺杂区包括横向交替的第一 背掺杂区和第二背掺杂区，并且其中所述第一背掺杂区包括与所述第二背掺杂区和所述背景掺杂区不同的电荷类型; 以及将背金属接触层设置在所述半导体晶片的所述背表面上，其中所述背金属接触层在所述第一背掺杂区域和所述第二背掺杂区域上对齐，并且被配置为传导来自所述第一背掺杂区域和所述第二背掺杂区域的电荷。