SUBSTRATE PROCESSING SYSTEM AND METHOD
    2.
    发明申请
    SUBSTRATE PROCESSING SYSTEM AND METHOD 审中-公开
    基板加工系统及方法

    公开(公告)号:WO2013070978A4

    公开(公告)日:2013-09-26

    申请号:PCT/US2012064241

    申请日:2012-11-08

    Abstract: A system for processing substrates has a vacuum enclosure and a processing chamber situated to process wafers in a processing zone inside the vacuum enclosure. Two rail assemblies are provided, one on each side of the processing zone. Two chuck arrays ride, each on one of the rail assemblies, such that each is cantilevered on one rail assemblies and support a plurality of chucks. The rail assemblies are coupled to an elevation mechanism that places the rails in upper position for processing and at lower position for returning the chuck assemblies for loading new wafers. A pickup head assembly loads wafers from a conveyor onto the chuck assemblies. The pickup head has plurality of electrostatic chucks that pick up the wafers from the front side of the wafers.

    Abstract translation: 用于处理衬底的系统具有真空外壳和位于处理真空外壳内的处理区中的晶片的处理室。 提供两个轨道组件,一个在处理区域的每一侧。 两个卡盘阵列,每个在一个导轨组件上,使得每个卡盘阵列悬挂在一个导轨组件上并支撑多个卡盘。 轨道组件联接到升降机构,其将轨道放置在用于处理的上部位置,并且在较低位置处返回用于装载新晶片的卡盘组件。 拾取头组件将晶片从传送器装载到卡盘组件上。 拾取头具有从晶片的前侧拾取晶片的多个静电卡盘。

    SUBSTRATE PROCESSING SYSTEM AND METHOD

    公开(公告)号:SG10201508582WA

    公开(公告)日:2015-11-27

    申请号:SG10201508582W

    申请日:2012-11-08

    Applicant: INTEVAC INC

    Abstract: A system for processing substrates has a vacuum enclosure and a processing chamber situated to process wafers in a processing zone inside the vacuum enclosure. Two rail assemblies are provided, one on each side of the processing zone. Two chuck arrays ride, each on one of the rail assemblies, such that each is cantilevered on one rail assemblies and support a plurality of chucks. The rail assemblies are coupled to an elevation mechanism that places the rails in upper position for processing and at lower position for returning the chuck assemblies for loading new wafers. A pickup head assembly loads wafers from a conveyor onto the chuck assemblies. The pickup head has plurality of electrostatic chucks that pick up the wafers from the front side of the wafers. Cooling channels in the processing chucks are used to create air cushion to assist in aligning the wafers when delivered by the pickup head.

    AN ADJUSTABLE SHADOW MASK ASSEMBLY FOR USE IN SOLAR CELL FABRICATIONS

    公开(公告)号:SG183267A1

    公开(公告)日:2012-09-27

    申请号:SG2012059382

    申请日:2011-02-09

    Applicant: INTEVAC INC

    Abstract: An adjustable shadow mask implantation system comprising: an ion source configured to provide ions; and an shadow mask assembly configured to selectively allow ions from the ion source to pass therethrough to a substrate where they are implanted, wherein the shadow mask assembly is configured to adjust between a first position and a second position, wherein the shadow mask assembly enables ion implantation of multiple substantially parallel lines absent any lines with an intersecting orientation with respect to the multiple substantially parallel lines when set in the first position, and wherein the shadow mask assembly enables ion implantation of multiple substantially parallel lines and a line with an intersecting orientation with respect to the multiple substantially parallel lines when set in the second position.

    SUBSTRATE PROCESSING SYSTEM AND METHOD

    公开(公告)号:SG11201402177XA

    公开(公告)日:2014-06-27

    申请号:SG11201402177X

    申请日:2012-11-08

    Abstract: A system for processing substrates has a vacuum enclosure and a processing chamber situated to process wafers in a processing zone inside the vacuum enclosure. Two rail assemblies are provided, one on each side of the processing zone. Two chuck arrays ride, each on one of the rail assemblies, such that each is cantilevered on one rail assemblies and support a plurality of chucks. The rail assemblies are coupled to an elevation mechanism that places the rails in upper position for processing and at lower position for returning the chuck assemblies for loading new wafers. A pickup head assembly loads wafers from a conveyor onto the chuck assemblies. The pickup head has plurality of electrostatic chucks that pick up the wafers from the front side of the wafers. Cooling channels in the processing chucks are used to create air cushion to assist in aligning the wafers when delivered by the pickup head.

    PLASMA GRID IMPLANT SYSTEM FOR USE IN SOLAR CELL FABRICATIONS

    公开(公告)号:SG196827A1

    公开(公告)日:2014-02-13

    申请号:SG2014003446

    申请日:2010-06-23

    Applicant: INTEVAC INC

    Abstract: Amethod of ion implantation comprising: providing a plasmawithin a plasma region of a chamber; positively biasing a first grid plate,wherein the first grid plate comprises a plurality of apertures; negativelybiasing a second grid plate, wherein the second grid plate comprises aplurality of apertures: flowing ions from the plasma in theplasma region through the pertures in the positively-biased first gridplate; flowing at least a portion of the ions that flowedthrough the apertures in the positively-biased first grid plate through theapertures in the negatively-biased second grid plate; and implanting asubstrate with at least a portion of the ions that flowed through theapertures in the negatively-biased second grid plate. Fig. 1

    ADVANCED HIGH EFFICIENCY CRYSTALLINE SOLAR CELL FABRICATION METHOD

    公开(公告)号:SG186005A1

    公开(公告)日:2012-12-28

    申请号:SG2012084331

    申请日:2010-03-19

    Applicant: INTEVAC INC

    Abstract: ADVANCED HIGH EFFICIENCY CRYSTALLINE SOLAR CELL FABRICATION METHOD5 A method of fabricating a solar cell comprising: providing a semiconducting wafer having a front surface, a back surface, and a background doped region; performing a set of ion implantations of dopant into the semiconducting wafer to form a back altematingly-doped region extending from the back surface of the semiconducting wafer to a location between the back surface and the front surface, wherein the back doped10 region comprises laterally alternating first back doped regions and second back doped regions, and wherein the first back doped regions comprise a different charge type than the second back doped regions and the background doped region; and disposing a back metal contact layer onto the back surface of the semiconducting wafer, wherein the back metal contact layer is aligned over the first and second back doped regions and is15 configured to conduct electrical charge from the first and second back doped regions. Fig. 1

    IMPLANT MASKING AND ALIGNMENT
    10.
    发明专利

    公开(公告)号:SG11201700675UA

    公开(公告)日:2017-02-27

    申请号:SG11201700675U

    申请日:2015-08-05

    Applicant: INTEVAC INC

    Abstract: System and method to align a substrate under a shadow mask. A substrate holder has alignment mechanism, such as rollers, that is made to abut against an alignment straight edge. The substrate is then aligned with respect to the straight edge and is chucked to the substrate holder. The substrate holder is then transported into a vacuum processing chamber, wherein it is made to abut against a mask straight edge to which the shadow mask is attached and aligned to. Since the substrate was aligned to an alignment straight edge, and since the mask is aligned to the mask straight edge that is precisely aligned to the alignment straight edge, the substrate is perfectly aligned to the mask.

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