公开(公告)号：US11543878B2

公开(公告)日：2023-01-03

申请号：US17042804

申请日：2018-05-01

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Eric Dehaemer ,  Alexander Gendler ,  Nadav Shulman ,  Krishnakanth Sistla ,  Nir Rosenzweig ,  Ankush Varma ,  Ariel Szapiro ,  Arye Albahari ,  Ido Melamed ,  Nir Misgav ,  Vivek Garg ,  Nimrod Angel ,  Adwait Purandare ,  Elkana Korem

IPC: G06F1/32 ,  G06F9/4401 ,  G06F1/329 ,  G06F1/3206 ,  G06F9/30 ,  G06F9/48

Abstract: A local power control arbiter is provided to interface with a global power control unit of a processing platform having a plurality of processing entities. The local power control arbiter controls a local processing unit of the processing platform. The local power arbiter has an interface to receive from the global power control unit, a local performance limit allocated to the local processing unit depending on a global power control evaluation and processing circuitry to determine any change to one or more processing conditions prevailing in the local processing unit on a timescale shorter than a duration for which the local performance limit is applied to the local processing unit by the global power control unit and to select a performance level for the local processing unit depending on both the local performance limit and the determined change, if any, to the prevailing processing conditions on the local processing unit.

公开(公告)号：US20220413720A1

公开(公告)日：2022-12-29

申请号：US17359334

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Adwait Purandare ,  Ian Steiner ,  Vasudevan Srinivasan ,  Ankush Varma ,  Nikhil Gupta ,  Stanley Chen

IPC: G06F3/06

Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to receive a mapping of multiple virtual partitions to sets of the processing engines, and in response to a receipt of the mapping of multiple of virtual partitions: access a power limit table for the processor, and generate multiple virtual partition power limit tables based on the power limit table for the processor, where each virtual partition power limit table is associated with a different virtual partition. Other embodiments are described and claimed.

公开(公告)号：US11366506B2

公开(公告)日：2022-06-21

申请号：US16691873

申请日：2019-11-22

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  David Pawlowski ,  Adwait Purandare ,  Ankush Varma

IPC: G06F1/32 ,  G06F1/3234

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

公开(公告)号：US20220100247A1

公开(公告)日：2022-03-31

申请号：US17033753

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Vivek Garg ,  Ankush Varma ,  Krishnakanth Sistla ,  Nikhil Gupta ,  Nikethan Shivanand Baligar ,  Stephen Wang ,  Nilanjan Palit ,  Timothy Kam ,  Adwait Purandare ,  Ujjwal Gupta ,  Stanley Chen ,  Dorit Shapira ,  Shruthi Venugopal ,  Suresh Chemudupati ,  Rupal Parikh ,  Eric Dehaemer ,  Pavithra Sampath ,  Phani Kumar Kandula ,  Yogesh Bansal ,  Dean Mulla ,  Michael Tulanowski ,  Stephen Haake ,  Andrew Herdrich ,  Ripan Das

IPC: G06F1/28 ,  G06F1/30 ,  G06F13/20

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

公开(公告)号：US20200089308A1

公开(公告)日：2020-03-19

申请号：US16691873

申请日：2019-11-22

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  David Pawlowski ,  Adwait Purandare ,  Ankush Varma

IPC: G06F1/3234

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.