公开(公告)号：US12093100B2

公开(公告)日：2024-09-17

申请号：US17033753

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Vivek Garg ,  Ankush Varma ,  Krishnakanth Sistla ,  Nikhil Gupta ,  Nikethan Shivanand Baligar ,  Stephen Wang ,  Nilanjan Palit ,  Timothy Yee-Kwong Kam ,  Adwait Purandare ,  Ujjwal Gupta ,  Stanley Chen ,  Dorit Shapira ,  Shruthi Venugopal ,  Suresh Chemudupati ,  Rupal Parikh ,  Eric Dehaemer ,  Pavithra Sampath ,  Phani Kumar Kandula ,  Yogesh Bansal ,  Dean Mulla ,  Michael Tulanowski ,  Stephen Paul Haake ,  Andrew Herdrich ,  Ripan Das ,  Nazar Syed Haider ,  Aman Sewani

IPC: G06F1/28 ,  G06F1/30 ,  G06F13/20

CPC classification number: G06F1/28 ,  G06F1/30 ,  G06F13/20 ,  G06F2213/40

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

公开(公告)号：US20250004536A1

公开(公告)日：2025-01-02

申请号：US18216456

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Adwait Purandare ,  Ankush Varma ,  Nilanjan Palit ,  Yuval Bustan ,  Eran Barnett ,  Eliezer Weissman ,  Stanley Chen ,  Arjan Van De Ven

IPC: G06F1/3296 ,  G06F1/324

Abstract: Techniques and mechanisms for determining operation a processor core which is in a common power delivery domain with one or more other processor cores. In an embodiment, an execution of instructions by a first core of a processor module is selectively throttled based on the detection of a single violation condition. The throttling is performed while the cores of the processor module are each maintained in a current power state. The single violation condition comprises a violation of a test criteria by the first core, while the one or more other cores of the module each satisfy the test criteria. In the case of a multiple violation condition, each core of the processor module is transitioned from one power state to another power state. In another embodiment, the test criteria includes or is otherwise based on a threshold level of a dynamic capacitance for a given core.

公开(公告)号：US20220413720A1

公开(公告)日：2022-12-29

申请号：US17359334

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Adwait Purandare ,  Ian Steiner ,  Vasudevan Srinivasan ,  Ankush Varma ,  Nikhil Gupta ,  Stanley Chen

IPC: G06F3/06

Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to receive a mapping of multiple virtual partitions to sets of the processing engines, and in response to a receipt of the mapping of multiple of virtual partitions: access a power limit table for the processor, and generate multiple virtual partition power limit tables based on the power limit table for the processor, where each virtual partition power limit table is associated with a different virtual partition. Other embodiments are described and claimed.

公开(公告)号：US20220100247A1

公开(公告)日：2022-03-31

申请号：US17033753

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Vivek Garg ,  Ankush Varma ,  Krishnakanth Sistla ,  Nikhil Gupta ,  Nikethan Shivanand Baligar ,  Stephen Wang ,  Nilanjan Palit ,  Timothy Kam ,  Adwait Purandare ,  Ujjwal Gupta ,  Stanley Chen ,  Dorit Shapira ,  Shruthi Venugopal ,  Suresh Chemudupati ,  Rupal Parikh ,  Eric Dehaemer ,  Pavithra Sampath ,  Phani Kumar Kandula ,  Yogesh Bansal ,  Dean Mulla ,  Michael Tulanowski ,  Stephen Haake ,  Andrew Herdrich ,  Ripan Das

IPC: G06F1/28 ,  G06F1/30 ,  G06F13/20

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

公开(公告)号：US20230195918A1

公开(公告)日：2023-06-22

申请号：US17645070

申请日：2021-12-20

Applicant: Intel Corporation

Inventor： Stanley Chen ,  Vivek Garg ,  Ankush Varma ,  Eric J. Dehaemer ,  Johan van de Groenendaal

IPC: G06F21/62 ,  G06F9/30

CPC classification number: G06F21/6218 ,  G06F9/30101

Abstract: In an embodiment, a processor may include at least one processing engine to execute instructions, and a register interface circuit coupled to the at least one processing engine. The register interface circuit may be to: receive a request to access a register associated with a feature of the processor; determine whether the requested access is authorized based at least in part on an entry of an access structure, the access structure to store a plurality of entries associated with a plurality of features of the processor; and in response to a determination that the requested access is authorized by the access structure, perform the requested access of the register associated with the feature. Other embodiments are described and claimed.