公开(公告)号：US20240028101A1

公开(公告)日：2024-01-25

申请号：US18477823

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  David Pawlowski ,  Adwait Purandare ,  Ankush Varma

IPC: G06F1/3234 ,  G06F1/324 ,  G06F1/3206

CPC classification number: G06F1/3234 ,  G06F1/324 ,  G06F1/3206

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

公开(公告)号：US11853144B2

公开(公告)日：2023-12-26

申请号：US17664083

申请日：2022-05-19

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  David Pawlowski ,  Adwait Purandare ,  Ankush Varma

IPC: G06F1/32 ,  G06F1/3234 ,  G06F1/324 ,  G06F1/3206

CPC classification number: G06F1/3234 ,  G06F1/324 ,  G06F1/3206

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

公开(公告)号：US20250004536A1

公开(公告)日：2025-01-02

申请号：US18216456

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Adwait Purandare ,  Ankush Varma ,  Nilanjan Palit ,  Yuval Bustan ,  Eran Barnett ,  Eliezer Weissman ,  Stanley Chen ,  Arjan Van De Ven

IPC: G06F1/3296 ,  G06F1/324

Abstract: Techniques and mechanisms for determining operation a processor core which is in a common power delivery domain with one or more other processor cores. In an embodiment, an execution of instructions by a first core of a processor module is selectively throttled based on the detection of a single violation condition. The throttling is performed while the cores of the processor module are each maintained in a current power state. The single violation condition comprises a violation of a test criteria by the first core, while the one or more other cores of the module each satisfy the test criteria. In the case of a multiple violation condition, each core of the processor module is transitioned from one power state to another power state. In another embodiment, the test criteria includes or is otherwise based on a threshold level of a dynamic capacitance for a given core.

公开(公告)号：US12124314B2

公开(公告)日：2024-10-22

申请号：US17207299

申请日：2021-03-19

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Adwait Purandare ,  Ankush Varma ,  Nazar Haider ,  Daniela Kaufman ,  Gilad Bomstein ,  Shlomo Attias ,  Amit Gabai ,  Ariel Szapiro

IPC: G06F1/324 ,  G06F1/28 ,  G06F21/55 ,  G06F21/56 ,  G06F21/71 ,  G06F21/81

CPC classification number: G06F1/324 ,  G06F1/28 ,  G06F21/554 ,  G06F21/566 ,  G06F21/71 ,  G06F21/81 ,  G06F2221/034

Abstract: An adaptive or dynamic power virus control scheme (hardware and/or software) that dynamically adjusts maximum dynamic capacitance (CdynMax) and corresponding maximum frequency (P0nMax) setting per application executed on a processor core. A power management unit monitors telemetry such as a number of throttled cycles due to CdynMax threshold excursions cycles for the processor core and a cost of average cycle Cdyn cost for the processor core. As the number of throttling cycles increases for the processor core, the aCode firmware of the power management unit decides to increase the Cdyn level or threshold for that core (e.g., to make the threshold less aggressive). As the average Cdyn cost over a number of cycles becomes lower than a threshold, aCode adjusts the threshold to a lower threshold (e.g., more aggressive threshold) and lower Cdyn.

公开(公告)号：US12093100B2

公开(公告)日：2024-09-17

申请号：US17033753

申请日：2020-09-26

Applicant: Intel Corporation

Inventor： Vivek Garg ,  Ankush Varma ,  Krishnakanth Sistla ,  Nikhil Gupta ,  Nikethan Shivanand Baligar ,  Stephen Wang ,  Nilanjan Palit ,  Timothy Yee-Kwong Kam ,  Adwait Purandare ,  Ujjwal Gupta ,  Stanley Chen ,  Dorit Shapira ,  Shruthi Venugopal ,  Suresh Chemudupati ,  Rupal Parikh ,  Eric Dehaemer ,  Pavithra Sampath ,  Phani Kumar Kandula ,  Yogesh Bansal ,  Dean Mulla ,  Michael Tulanowski ,  Stephen Paul Haake ,  Andrew Herdrich ,  Ripan Das ,  Nazar Syed Haider ,  Aman Sewani

IPC: G06F1/28 ,  G06F1/30 ,  G06F13/20

CPC classification number: G06F1/28 ,  G06F1/30 ,  G06F13/20 ,  G06F2213/40

Abstract: Hierarchical Power Management (HPM) architecture considers the limits of scaling on a power management controller, the autonomy at each die, and provides a unified view of the package to a platform. At a simplest level, HPM architecture has a supervisor and one or more supervisee power management units (PMUs) that communicate via at least two different communication fabrics. Each PMU can behave as a supervisor for a number of supervisee PMUs in a particular domain. HPM addresses these needs for products that comprise a collection of dice with varying levels of power and thermal management capabilities and needs. HPM serves as a unified mechanism than can span collection of dice of varying capability and function, which together form a traditional system-on-chip (SoC). HPM provides a basis for managing power and thermals across a diverse set of dice.

公开(公告)号：US11775298B2

公开(公告)日：2023-10-03

申请号：US16933369

申请日：2020-07-20

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Srihari Makineni ,  Shubha Bommalingaiahnapallya ,  Neelam Chandwani ,  Rany T. Elsayed ,  Udayan Mukherjee ,  Lokpraveen Mosur ,  Adwait Purandare

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30036 ,  G06F9/3887

Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores. These capabilities enhance performance and provides flexibility to handle a variety of applications requiring use of advanced AVX/AMX instructions to support accelerated workloads.

公开(公告)号：US20230148150A1

公开(公告)日：2023-05-11

申请号：US17664083

申请日：2022-05-19

Applicant: Intel Corporation

Inventor： Jianwei Dai ,  David Pawlowski ,  Adwait Purandare ,  Ankush Varma

IPC: G06F1/3234

CPC classification number: G06F1/3234

Abstract: In one embodiment, a processor includes a plurality of intellectual property (IP) circuits, each to execute instructions and including a local control circuit to enable the IP circuit to operate at a level above a local current budget for the IP circuit, unless the processor is undergoing a global violation. The processor may further include a power controller coupled to the plurality of IP circuits. The power controller may include a control circuit to receive request information from the plurality of IP circuits and, based at least in part on the request information, determine that the processor is undergoing the global violation when a global current budget is exceeded. Other embodiments are described and claimed.

公开(公告)号：US20210208659A1

公开(公告)日：2021-07-08

申请号：US17207299

申请日：2021-03-19

Applicant: Intel Corporation

Inventor： Alexander Gendler ,  Adwait Purandare ,  Ankush Varma ,  Nazar Haider ,  Daniela Kaufman ,  Gilad Bomstein ,  Shlomo Attias ,  Amit Gabai ,  Ariel Szapiro

IPC: G06F1/324 ,  G06F21/55 ,  G06F1/28

Abstract: An adaptive or dynamic power virus control scheme (hardware and/or software) that dynamically adjusts maximum dynamic capacitance (CdynMax) and corresponding maximum frequency (POnMax) setting per application executed on a processor core. A power management unit monitors telemetry such as a number of throttled cycles due to CdynMax threshold excursions cycles for the processor core and a cost of average cycle Cdyn cost for the processor core. As the number of throttling cycles increases for the processor core, the aCode firmware of the power management unit decides to increase the Cdyn level or threshold for that core (e.g., to make the threshold less aggressive). As the average Cdyn cost over a number of cycles becomes lower than a threshold, aCode adjusts the threshold to a lower threshold (e.g., more aggressive threshold) and lower Cdyn.

公开(公告)号：US12282377B2

公开(公告)日：2025-04-22

申请号：US17358224

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： Pritesh P. Shah ,  Suresh Chemudupati ,  Alexander Gendler ,  David Hunt ,  Christopher M. Macnamara ,  Ofer Nathan ,  Adwait Purandare ,  Ankush Varma

IPC: G06F1/3287 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/50

Abstract: A hardware controller within a core of a processor is described. The hardware controller includes telemetry logic to generate telemetry data that indicates an activity state of the core; core stall detection logic to determine, based on the telemetry data from the telemetry logic, whether the core is in an idle loop state; and a power controller that, in response to the core stall detection logic determining that the core is in the idle loop state, is to decrease a power mode of the core from a first power mode associated with a first set of power settings to a second power mode associated with a second set of power settings.

公开(公告)号：US12248783B2

公开(公告)日：2025-03-11

申请号：US18369082

申请日：2023-09-15

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Srihari Makineni ,  Shubha Bommalingaiahnapallya ,  Neelam Chandwani ,  Rany T. Elsayed ,  Udayan Mukherjee ,  Lokpraveen Mosur ,  Adwait Purandare

IPC: G06F1/3203 ,  G06F9/30 ,  G06F9/38

Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores. These capabilities enhance performance and provides flexibility to handle a variety of applications requiring use of advanced AVX/AMX instructions to support accelerated workloads.