公开(公告)号：US20230145229A1

公开(公告)日：2023-05-11

申请号：US17522342

申请日：2021-11-09

Applicant: Intel Corporation

Inventor： Nicole K. Thomas ,  Ashish Agrawal ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Ehren Mannebach ,  Willy Rachmady ,  Marko Radosavljevic

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/786 ,  H01L27/088

CPC classification number: H01L29/42392 ,  H01L29/0665 ,  H01L29/78696 ,  H01L27/088

Abstract: Techniques are provided herein to form semiconductor devices having backside contacts. Sacrificial plugs are formed first within a substrate at particular locations to align with source and drain regions during a later stage of processing. Another wafer is subsequently bonded to the surface of the substrate and is thinned to effectively transfer different material layers to the top surface of the substrate. One of the transferred layers acts as a seed layer for the growth of additional semiconductor material used to form semiconductor devices. The source and drain regions of the semiconductor devices are sufficiently aligned over the previously formed sacrificial plugs. A backside portion of the substrate may be removed to expose the sacrificial plugs from the backside. Removal of the plugs and replacement of the recesses left behind with conductive material forms the conductive backside contacts to the source or drain regions.

公开(公告)号：US20230134379A1

公开(公告)日：2023-05-04

申请号：US17517925

申请日：2021-11-03

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Urusa Alaan ,  Susmita Ghose ,  Rambert Nahm ,  Natalie Briggs ,  Nicole K. Thomas ,  Willy Rachmady ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/8234

Abstract: Techniques are provided herein to form gate-all-around (GAA) semiconductor devices, such as those having a stacked transistor configuration. In one example case, two different semiconductor devices may both be GAA transistors each having any number of nanoribbons extending in the same (e.g., horizontal) direction where one device is located vertically above the other device. An internal spacer structure extends between the nanoribbons of both devices along the vertical direction, where the spacer structure includes one or more rib features between the two devices. A gate structure that includes one or more gate dielectric layers and one or more gate electrode layers may be formed around the nanoribbons of both devices, in some cases. In other cases, a split-gate configuration is used where upper and lower gate structures are separated by an isolation structure. Forksheet transistors and other GAA configurations may be formed using the techniques as well.

公开(公告)号：US11573798B2

公开(公告)日：2023-02-07

申请号：US16290544

申请日：2019-03-01

Applicant: Intel Corporation

Inventor： Aaron D. Lilak ,  Gilbert W. Dewey ,  Willy Rachmady ,  Rishabh Mehandru ,  Ehren Mannebach ,  Cheng-Ying Huang ,  Anh Phan ,  Patrick Morrow

IPC: H01L29/772 ,  G06F9/30 ,  G06F9/34 ,  H01L29/78 ,  H01L29/66 ,  H01L29/786 ,  H01L29/775

Abstract: Disclosed herein are stacked transistors with different gate lengths in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, with two different device strata having different gate lengths.

公开(公告)号：US11469323B2

公开(公告)日：2022-10-11

申请号：US16140971

申请日：2018-09-25

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Sean T. Ma ,  Harold Kennel ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/423 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28

Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.

公开(公告)号：US11348916B2

公开(公告)日：2022-05-31

申请号：US16024076

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Anh Phan ,  Ehren Mannebach ,  Cheng-Ying Huang ,  Stephanie A. Bojarski ,  Gilbert Dewey ,  Orb Acton ,  Willy Rachmady

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/08 ,  H01L21/762 ,  H01L23/528 ,  H01L29/78 ,  H01L29/06

Abstract: Stacked transistor structures having a conductive interconnect between upper and lower transistors. In an embodiment, the interconnect is formed by first provisioning a protective layer over an area to be protected (gate dielectric or other sensitive material) of upper transistor, and then etching material adjacent and below the protected area to expose an underlying contact point of lower transistor. A metal is deposited into the void created by the etch to provide the interconnect. The protective layer is resistant to the etch process and is preserved in the structure, and in some cases may be utilized as a work-function metal. In an embodiment, the protective layer is formed by deposition of reactive semiconductor and metal material layers which are subsequently transformed into a work function metal or work function metal-containing compound. A remnant of unreacted reactive semiconductor material may be left in structure and collinear with protective layer.

公开(公告)号：US11257904B2

公开(公告)日：2022-02-22

申请号：US16024706

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Tahir Ghani ,  Jack Kavalieros ,  Anand Murthy ,  Harold Kennel ,  Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Sean Ma ,  Nicholas Minutillo

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US11049773B2

公开(公告)日：2021-06-29

申请号：US16320425

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Matthew V. Metz ,  Sean T. Ma ,  Cheng-Ying Huang ,  Tahir Ghani ,  Anand S. Murthy ,  Harold W. Kennel ,  Nicholas G. Minutillo ,  Jack T. Kavalieros ,  Willy Rachmady

IPC: H01L29/06 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/66 ,  H01L29/78

Abstract: A transistor device comprising a channel disposed on a substrate between a source and a drain, a gate electrode disposed on the channel, wherein the channel comprises a channel material that is separated from a body of the same material on a substrate. A method comprising forming a trench in a dielectric layer on an integrated circuit substrate, the trench comprising dimensions for a transistor body including a width; depositing a spacer layer in a portion of the trench, the spacer layer narrowing the width of the trench; forming a channel material in the trench through the spacer layer; recessing the dielectric layer to define a first portion of the channel material exposed and a second portion of the channel material in the trench; and separating the first portion of the channel material from the second portion of the channel material.

公开(公告)号：US20200295127A1

公开(公告)日：2020-09-17

申请号：US16351921

申请日：2019-03-13

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Aaron D. Lilak ,  Anh Phan ,  Cheng-Ying Huang ,  Gilbert W. Dewey ,  Patrick Morrow ,  Rishabh Mehandru ,  Roza Kotlyar ,  Sean T. Ma ,  Willy Rachmady

IPC: H01L29/04 ,  H01L29/78 ,  H01L29/06 ,  H01L27/092 ,  H01L25/11 ,  H01L23/00 ,  H01L23/522 ,  H01L29/16 ,  H01L29/20 ,  H01L21/8238 ,  H01L29/66

Abstract: Disclosed herein are stacked transistors with different crystal orientations in different device strata, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein the channel materials in at least some of the strata have different crystal orientations.

公开(公告)号：US20200098925A1

公开(公告)日：2020-03-26

申请号：US16140971

申请日：2018-09-25

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Sean T. Ma ,  Harold Kennel ,  Tahir Ghani

IPC: H01L29/78 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51 ,  H01L21/28 ,  H01L29/66

Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.

公开(公告)号：US12288803B2

公开(公告)日：2025-04-29

申请号：US18540544

申请日：2023-12-14

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Nicholas G. Minutillo ,  Sean T. Ma ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani ,  Gilbert Dewey

IPC: H01L29/06 ,  H01L29/205 ,  H01L29/423 ,  H01L29/78

Abstract: A transistor includes a body of semiconductor material, where the body has laterally opposed body sidewalls and a top surface. A gate structure contacts the top surface of the body. A source region contacts a first one of the laterally opposed body sidewalls and a drain region contacts a second one of the laterally opposed body sidewalls. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).