公开(公告)号：US12224337B2

公开(公告)日：2025-02-11

申请号：US17132951

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Michael Beumer ,  Robert Ehlert ,  Nicholas Minutillo ,  Michael Robinson ,  Patrick Wallace ,  Peter Wells

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66

Abstract: III-N e-mode high electron mobility transistors (HEMTs) including a dopant diffusion spacer between an impurity-doped III-N material layer and a III-N polarization layer of the HEMT material stack. The spacer may be a substantially undoped III-N material, such as GaN. With the diffusion spacer, P-type impurities within the pGaN are setback from the polarization layer sufficiently to avoid significant levels of P-type impurities from entering the III-N material interface where the 2DEG resides. With the diffusion spacer, clustering of impurities near the 2DEG may be avoided and a III-N e-mode HEMT may achieve higher drive currents.

公开(公告)号：US11257904B2

公开(公告)日：2022-02-22

申请号：US16024706

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Tahir Ghani ,  Jack Kavalieros ,  Anand Murthy ,  Harold Kennel ,  Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Sean Ma ,  Nicholas Minutillo

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/205 ,  H01L29/417 ,  H01L29/66 ,  H01L21/02 ,  H01L29/78

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device having a channel area including a channel III-V material, and a source area including a first portion and a second portion of the source area. The first portion of the source area includes a first III-V material, and the second portion of the source area includes a second III-V material. The channel III-V material, the first III-V material and the second III-V material may have a same lattice constant. Moreover, the first III-V material has a first bandgap, and the second III-V material has a second bandgap, the channel III-V material has a channel III-V material bandgap, where the channel material bandgap, the second bandgap, and the first bandgap form a monotonic sequence of bandgaps. Other embodiments may be described and/or claimed.

公开(公告)号：US11508577B2

公开(公告)日：2022-11-22

申请号：US16024694

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady ,  Sean Ma ,  Nicholas Minutillo ,  Cheng-Ying Huang ,  Tahir Ghani ,  Jack Kavalieros ,  Anand Murthy ,  Harold Kennel

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/04 ,  H01L29/78 ,  H01L27/12

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. Embodiments herein may present a semiconductor device including a substrate and an insulator layer above the substrate. A channel area may include an III-V material relaxed grown on the insulator layer. A source area may be above the insulator layer, in contact with the insulator layer, and adjacent to a first end of the channel area. A drain area may be above the insulator layer, in contact with the insulator layer, and adjacent to a second end of the channel area that is opposite to the first end of the channel area. The source area or the drain area may include one or more seed components including a seed material with free surface. Other embodiments may be described and/or claimed.

公开(公告)号：US20220199816A1

公开(公告)日：2022-06-23

申请号：US17132951

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Michael Beumer ,  Robert Ehlert ,  Nicholas Minutillo ,  Michael Robinson ,  Patrick Wallace ,  Peter Wells

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66 ,  H01L29/205

Abstract: III-N e-mode high electron mobility transistors (HEMTs) including a dopant diffusion spacer between an impurity-doped III-N material layer and a III-N polarization layer of the HEMT material stack. The spacer may be a substantially undoped III-N material, such as GaN. With the diffusion spacer, P-type impurities within the pGaN are setback from the polarization layer sufficiently to avoid significant levels of P-type impurities from entering the III-N material interface where the 2DEG resides. With the diffusion spacer, clustering of impurities near the 2DEG may be avoided and a III-N e-mode HEMT may achieve higher drive currents.

公开(公告)号：US11276694B2

公开(公告)日：2022-03-15

申请号：US16139684

申请日：2018-09-24

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Matthew Metz ,  Gilbert Dewey ,  Nicholas Minutillo ,  Cheng-Ying Huang ,  Jack Kavalieros ,  Anand Murthy ,  Tahir Ghani

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L29/207

Abstract: An integrated circuit with at least one transistor is formed using a buffer structure on the substrate. The buffer structure includes one or more layers of buffer material and comprises indium, gallium, and phosphorous. A ratio of indium to gallium in the buffer structure increases from a lower value to a higher value such that the buffer structure has small changes in lattice constant to control relaxation and defects. A source and a drain are on top of the buffer structure and a body of Group III-V semiconductor material extends between and connects the source and the drain. A gate structure wrapped around the body, the gate structure including a gate electrode and a gate dielectric, wherein the gate dielectric is between the body and the gate electrode.

公开(公告)号：US11695081B2

公开(公告)日：2023-07-04

申请号：US16024701

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Sean Ma ,  Nicholas Minutillo ,  Cheng-Ying Huang ,  Tahir Ghani ,  Jack Kavalieros ,  Anand Murthy ,  Harold Kennel ,  Gilbert Dewey ,  Matthew Metz ,  Willy Rachmady

IPC: H01L29/786 ,  H01L29/205 ,  H01L29/66 ,  H01L29/04 ,  H01L29/423

CPC classification number: H01L29/78696 ,  H01L29/045 ,  H01L29/205 ,  H01L29/42392 ,  H01L29/66462

Abstract: Embodiments herein describe techniques, systems, and method for a semiconductor device. A semiconductor device may include isolation areas above a substrate to form a trench between the isolation areas. A first buffer layer is over the substrate, in contact with the substrate, and within the trench. A second buffer layer is within the trench over the first buffer layer, and in contact with the first buffer layer. A channel area is above the first buffer layer, above a portion of the second buffer layer that are below a source area or a drain area, and without being vertically above a portion of the second buffer layer. In addition, the source area or the drain area is above the second buffer layer, in contact with the second buffer layer, and adjacent to the channel area. Other embodiments may be described and/or claimed.

公开(公告)号：US20230132548A1

公开(公告)日：2023-05-04

申请号：US17519429

申请日：2021-11-04

Applicant: Intel Corporation

Inventor： Atsunori Tanaka ,  Sanyam Bajaj ,  Michael S. Beumer ,  Robert Ehlert ,  Gregory P. McNerney ,  Nicholas Minutillo ,  Johann C. Rode ,  Suresh Vishwanath ,  Patrick M. Wallace

IPC: H01L29/778 ,  H01L29/20 ,  H01L29/66

Abstract: In one embodiment, a transistor is formed by a process comprising forming a buffer layer on a substrate, the buffer layer comprising a first group III-nitride (III-N) material (e.g., AlGaN), forming a channel layer on the buffer layer, the channel layer comprising a second III-N material (e.g., GaN), forming a polarization layer on the channel layer, the polarization layer comprising a third III-N material (e.g., AlGaN), flowing a p-type dopant precursor compound (e.g., Cp2Mg) after forming the polarization layer, forming a p-type doped layer (e.g., p-GaN) on the polarization layer, the p-type doped layer comprising a p-type dopant (e.g., Mg) and a fourth III-N material (e.g., GaN), forming a source region adjacent one end of the channel layer, and forming a drain region adjacent another end of the channel layer.

公开(公告)号：US11355621B2

公开(公告)日：2022-06-07

申请号：US16648199

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Sean Ma ,  Nicholas Minutillo ,  Tahir Ghani ,  Matthew V. Metz ,  Cheng-Ying Huang ,  Anand S. Murthy

IPC: H01L21/02 ,  H01L29/16 ,  H01L29/66 ,  H01L29/205 ,  H01L29/78

Abstract: Techniques and mechanisms for providing functionality of a non-planar device which includes a semiconductor body disposed on a dielectric layer and over an underlying subfin region. In an embodiment, the dielectric layer is disposed between, and adjoins each of, a first semiconductor material of the subfin region and a second semiconductor material of semiconductor body. The dielectric layer is an artefact of fabrication processing wherein an epitaxy of the semiconductor body is grown horizontally along a length of the subfin region. During such epitaxial growth, the dielectric layer prevents vertical growth of the second semiconductor material from the subfin region. Moreover, at least a portion of a dummy gate determines a shape of the semiconductor body. In another embodiment, formation of the semiconductor body is preceded by an etching to remove a section of a fin portion which is disposed over the subfin region.

公开(公告)号：US20200227539A1

公开(公告)日：2020-07-16

申请号：US16648199

申请日：2018-01-12

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Sean Ma ,  Nicholas Minutillo ,  Tahir Ghani ,  Matthew V. Metz ,  Cheng-Ying Huang ,  Anand S. Murthy

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/205

Abstract: Techniques and mechanisms for providing functionality of a non-planar device which includes a semiconductor body disposed on a dielectric layer and over an underlying subfin region. In an embodiment, the dielectric layer is disposed between, and adjoins each of, a first semiconductor material of the subfin region and a second semiconductor material of semiconductor body. The dielectric layer is an artefact of fabrication processing wherein an epitaxy of the semiconductor body is grown horizontally along a length of the subfin region. During such epitaxial growth, the dielectric layer prevents vertical growth of the second semiconductor material from the subfin region. Moreover, at least a portion of a dummy gate determines a shape of the semiconductor body. In another embodiment, formation of the semiconductor body is preceded by an etching to remove a section of a fin portion which is disposed over the subfin region.

公开(公告)号：US11935887B2

公开(公告)日：2024-03-19

申请号：US16368077

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Ryan Keech ,  Nicholas Minutillo ,  Anand Murthy ,  Aaron Budrevich ,  Peter Wells

IPC: H01L29/66 ,  H01L21/8234 ,  H01L23/00 ,  H01L27/088 ,  H01L29/08 ,  H01L29/167 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823475 ,  H01L24/09 ,  H01L24/17 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858 ,  H01L2224/0401

Abstract: Integrated circuit structures having source or drain structures with vertical trenches are described. In an example, an integrated circuit structure includes a fin having a lower fin portion and an upper fin portion. A gate stack is over the upper fin portion of the fin, the gate stack having a first side opposite a second side. A first source or drain structure includes an epitaxial structure embedded in the fin at the first side of the gate stack. A second source or drain structure includes an epitaxial structure embedded in the fin at the second side of the gate stack. The epitaxial structures of the first and second source or drain structures have a vertical trench centered therein. The first and second source or drain structures include silicon and a Group V dopant impurity.